Etching heterojunction interfaces

Details Etching heterojunction interfaces Etching heterojunction interfaces

2000-07-19

2003-07-01

Jones, Deborah (Department: 1773)

Stock material or miscellaneous articles

All metal or with adjacent metals

Composite; i.e., plural, adjacent, spatially distinct metal...

C428S642000, C428S699000, C428S704000, C257S200000

Reexamination Certificate

active

06586113

ABSTRACT:

TECHNICAL FIELD
This invention relates to systems and methods of manufacturing etchable heterojunction interfaces, and further relates to etched heterojunction structures.
BACKGROUND
A heterojunction (or heterostructure) is a junction formed between two adjacent dissimilar materials (e.g., two different semiconductor materials). Over the years, many devices have been proposed that exploit the unique properties and features of heterojunctions, properties that are not readily available from devices formed from a single material structure (e.g., homojunctions).
Typically, a heterojunction includes an interfacial parasitic layer (or heterojunction interface) that is composed of some or all of the constituent elements of the two adjacent materials forming the heterojunction. In many semiconductor heterojunction devices, it is necessary to etch through the heterojunction interface. Heterojunction interfaces must be etched, for example, to define active device layers (e.g., an emitter mesa in a heterojunction bipolar transistor) or to tune device parameters (e.g., the breakdown voltage and the threshold voltage of a heterojunction field effect transistor). For example, in the base contact region of a gallium arsenide/indium gallium phosphide (GaAs/InGaP) heterojunction bipolar transistor, the GaAs layer usually is removed with a selective etchant that stops at the InGaP layer. The InGaP layer subsequently is removed with a different selective etchant that preferably stops at the GaAs base. This process prevents the GaAs base from being over-etched. Similarly, in the gate recess region of a GaAs/InGaP field effect transistor, the GaAs cap usually is removed with a selective etchant that preferably stops at the InGaP layer. The InGaP layer subsequently is thinned with an etchant that etches through the InGaP layer at a relatively slow and predictable rate to set the threshold voltage of the field effect transistor.
To improve the speed and performance of semiconductor devices, there has been a constant push toward reducing devices sizes. As device dimensions shrink, however, the device elements, such as contacts, plugs, vias, and interconnect lines, also must shrink proportionately. In the current generation of semiconductor devices, circuit density has become so compact that device features have decreased below submicron dimensions. As device features shrink, it becomes more important to control critical device dimensions. Unfortunately, as device dimensions become smaller and spaced relatively closer together (e.g., less than 0.5 micron and even less than 0.25 micron), device manufacturing processes become less reliable, and device performance and processing yield tend to degrade significantly.
In order to control critical device dimensions, semiconductor device manufacturing processes typically rely on a high etch selectivity and a high aspect ratio between adjacent device layers. The selectivity of an etch process is the ratio of the etch rates of different materials. The aspect ratio of an etch process is the depth that the etch process can achieve while maintaining the requisite critical lateral dimensions. Generally, semiconductor device processing techniques have the ability to control the critical dimensions within acceptable tolerance ranges for devices with dimensions in the range of approximately 0.5-1.0 micron. However, as the dimensions decrease below this level, and especially at or below 0.25 micron, these processes often do not provide sufficient control over the critical dimensions due to poor etch selectivity and low aspect ratios.
SUMMARY
Prior device manufacturing efforts have focused on various parameters of device etching processes (e.g., etchant composition, etchant concentration, and etchant temperature) to control the dimensions and other physical properties of the devices being manufactured. The invention provides improved results by tailoring the structure of the heterojunction interface to respond to heterojunction etching processes with greater predictability and control.
In one aspect, the invention features a processing method in which a bottom layer is deposited on a substrate, a transition etch layer is deposited over the bottom layer, and a top layer is deposited over the transition etch layer. The transition etch layer substantially prevents the bottom layer and the top layer from forming a material characterized by a composition substantially different than the bottom layer and a substantially non-selective etchability with respect to the bottom layer.
As used herein, the “substantially non-selective etchability” of a first layer with respect to a second layer refers to the inability to etch the first layer with an etchant that is substantially selective with respect to the second layer. Similarly, the “substantially selective etchability” of a first layer with respect to a second layer refers to the ability to etch the first layer with an etchant that is substantially selective with respect to the second layer.
Embodiments of the invention may include one or more of the following features.
In some embodiments, the transition etch layer substantially prevents the bottom layer and the top layer from forming a material characterized by a composition substantially different than the top layer and a substantially non-selective etchability with respect to the top layer. The transition etch layer may be characterized by a substantially non-selective etchability with respect to the top layer. The transition etch layer may form with the top layer a top interfacial layer that is characterized by a substantially non-selective etchability with respect to the top layer. The transition etch layer may include two or more sub-layers.
In some embodiments, the top layer and the bottom layer are different compound semiconductors each formed from a respective combination of constituent elements, and the transition etch layer is a compound semiconductor formed from a combination of two or more but less than all of the constituent elements of the top layer and the bottom layer. In one embodiment, one of the top layer and the bottom layer is GaAs, the other of the top layer and the bottom layer is InGaP, and the transition etch layer is formed from GaP or a combination of GaP and GaAsP. In another embodiment, one of the top layer and the bottom layer is InGaAs, the other of the top layer and the bottom layer is InP, and the transition etch layer is formed from InAs or a combination of GaP and GaAs.
The transition etch layer preferably has a thickness that is less than about 10 nanometer (nm), and more preferably has a thickness between about 0.5 nm and about 5 nm.
In some embodiments, the top layer is etched with an etchant, and the transition etch layer preferably is etched with the same etchant. In one embodiment, a top interfacial layer formed between the top layer and the transition etch layer also may be etched with the same etchant with which the top layer was etched. In another embodiment, a bottom interfacial layer formed between the bottom layer and the transition etch layer also may be substantially etched with the same etchant with which the top layer was etched. In some embodiments, the transition etch layer is etched with an etchant that is selective to the bottom layer and different from the etchants used to etch the top layer and the bottom layer.
In another aspect, the invention features a composition of matter comprising a top layer, a bottom layer, and a transition etch layer disposed between the top layer and the bottom layer. The transition etch layer substantially prevents the bottom layer and the top layer from forming a material characterized by a composition substantially different than the bottom layer and a substantially non-selective etchability with respect to the bottom layer.
In another aspect, the invention features a composition of matter comprising a first layer of GaAs, a second layer of InGaP, a transition etch layer disposed between the first layer and the second layer, and a via. The via is etched through the transition etch layer, o

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