Semiconductor device manufacturing: process – Chemical etching – Liquid phase etching
Reexamination Certificate
2000-03-14
2004-01-27
Chen, Kin-Chan (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Liquid phase etching
C134S095100
Reexamination Certificate
active
06683007
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to etching and cleaning methods and etching and cleaning apparatuses used for semiconductor device fabrication and more particularly, to etching and cleaning methods of removing an unnecessary or undesired material or materials from a semiconductor wafer and etching and cleaning apparatuses used for performing the etching or cleaning method.
2. Description of the Prior Art
In the processes of fabricating semiconductor devices on a semiconductor wafer, various etching methods are usually used to remove unnecessary or undesired materials from the wafer and various cleaning methods are usually used to clean contaminants attached to the wafer or devices. In these cases, there is the need to remove unnecessary or undesired materials existing on the surface peripheral area of the wafer, on the back peripheral area of the wafer, or on the end face of the wafer.
Here, the “end face” means the end face of the wafer located between its surface and back and approximately perpendicular to them. The “surface peripheral area” means the area or region of the surface of the wafer between the device area and the end face. The device area is an area or region of the surface of the wafer in which desired semiconductor devices are formed. The “back peripheral area” means the area or region of the back of the wafer in which an undesired or unnecessary material or materials to be removed are present.
In recent years, copper (Cu) has been used as a wiring or interconnection material instead of aluminum (Al), because Cu is higher in conductivity than Al. In this case, Cu wiring lines are typically formed in trenches of a silicon dioxide (SiO
2
) film, which are usually realized by the step of forming the trenches in the SiO
2
film, the step of forming a Cu film on the SiO
2
film to cover the trenches by electroplating, and the step of selectively removing the Cu film to leave the same in the trenches by Chemical Mechanical Polishing (CMP). This method is termed the “damascene process”.
Next, the damascene process for the Cu wiring lines is explained in detail.
First, trenches are formed in a SiO
2
film to have a pattern for desired wiring lines by a known method, where the SiO
2
film is formed on or over a single-crystal silicon (Si) wafer or substrate. Second, a barrier metal film, which is made of meal such as tantalum (Ta) and tantalum nitride (TaN), is formed on the SiO
2
film to cover the trenches by sputtering. The barrier metal film is to prevent the Cu atoms from diffusing into the SiO
2
film. Third, a seed Cu film is formed on the barrier metal film by sputtering. Fourth, a wiring Cu film is formed on the seed Cu film by electroplating.
In the fourth step of forming the wiring Cu film by electroplating, a ring-shaped blocking member is placed on the surface of the wafer to surround the device area and then, a proper plating liquid or solution is supplied to the inside of the member. At this time, there is a possibility that the plating liquid leaks out of the member. If leakage of the liquid occurs, the wiring Cu film is formed not only in the device area but also in the surface peripheral area of the wafer. The wiring Cu film thus formed in the surface peripheral area is unnecessary and to be removed. The unnecessary Cu film tends to be detached from the SiO
2
film in the subsequent process or processes due to stress to thereby contaminate the production lines of the semiconductor device, because of weak adhesion of the plated Cu film to the SiO
2
film. As a result, the unnecessary Cu film needs to be removed.
Moreover, after the CMP process is completed, the Si wafer is contaminated by Cu wastes produced from the Cu film polished. The Cu wastes tend to diffuse into the SiO
2
film and the Si wafer due to subsequent heat treatment, thereby badly affecting the performance of the semiconductor devices formed in the device area. Since the Cu wastes adhere onto the surface and back peripheral areas and the end face of the wafer, they are difficult to be removed therefrom. Thus, the Cu wastes need to be removed by cleaning.
When the Si wafer is 8 inches in diameter, the distance between the edge of the device area and the end face of the wafer is typically set as, for example, approximately 5 mm. To expand the device area, it is preferred that the SiO
2
film (in which the Cu wiring lines are formed) is formed on the wafer to be expanded until the distance between the edge of the SiO
2
film and the end face is decreased to 1.5 mm to 2.0 mm. In this case, however, when the seed Cu film is deposited onto the barrier metal film over the whole wafer by sputtering in order to cover the whole SiO
2
film, it tends to cover not only the device area but also the surface and back peripheral areas and the end face of the wafer. Thus, if the plating liquid or solution supplied to the inside of the ring-shaped blocking member leaks out, the wiring Cu film tends to be formed on the seed film not only in the device area but also in the surface and back peripheral areas and the end face.
Since the wiring Cu film is formed on the seed Cu film, it is not separated or stripped off. However, the wiring Cu film existing on the end face of the wafer tends to be adhered onto the wafer carriers and/or the robot arms during transportation processes in the semiconductor device fabrication system. Thus, it tends to contaminate the transportation subsystem. This means that the wiring Cu film existing on the surface and back peripheral areas and the end face of the wafer needs to be removed before the wafer is transported to the next stage.
Furthermore, the removal of the above-described wiring Cu film requires good controllability. This is because the distance between the edge of the SiO
2
film and the end face is as short as 1.5 mm to 2 mm. The cleaning of the above-described Cu contaminants generated in the CMP process also necessitates similar good controllability.
To remove the undesired or unnecessary Cu film or contaminants explained above, various etching and cleaning methods have been developed and disclosed, two examples of which are shown in
FIGS. 1 and 2
.
In the prior-art cleaning/etching method as shown in
FIG. 1
, a protection film
112
having an etch-resistant property is selectively formed on the surface
110
A of a semiconductor wafer
110
to cover the entire device area formed thereon. Then, the wafer
110
with the film
112
is entirely immersed into an etching solution
114
stored in a suitable container
113
, thereby etching selectively the exposed area of the wafer
110
. Thus, the exposed area is cleaned. Thereafter, the film
112
is removed from the wafer
110
.
As the etching solution
114
, for example, a mixture of hydrogen fluoride (HF), hydrogen peroxide (H
2
O
2
), and water (H
2
O), which is often termed “Fluoric-Peroxide Mixture (FPM)”, may be used.
In the prior-art cleaning/etching method as shown in
FIG. 2
, a semiconductor wafer
110
is rotated in a horizontal plane by a proper rotating means while it is turned upside down. In this state, an etching solution
114
(e.g., FPM) is supplied downward toward the center of the back
110
B of the wafer
110
. At the same time as this, a protection gas
115
(e.g., nitrogen gas, N
2
) is supplied upward toward the center of the surface
110
A of the wafer
110
.
The solution
114
thus supplied onto the back
110
B moves outward to the end face
110
C of the wafer
110
along the back
110
B and then, flows along the vertical end face
110
C, and drops from the end face
110
C. Part of the solution
114
reaches the periphery of the surface
110
A and then, it is dropped therefrom.
The protection gas
115
thus supplied to the surface
110
A keeps the device area not to be contacted with the etching solution
114
. The solution
114
selectively etches the back
110
B, the end face
110
C, and the periphery of the surface
110
A, thereby cleaning them.
With the prior-art cleaning/etching method as shown in
FIG. 1
, there is a disadvantage th
Aoki Hidemitsu
Yamasaki Shinya
Chen Kin-Chan
NEC Corporation
Sughrue & Mion, PLLC
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