Patent
1981-11-12
1984-07-03
Edlow, Martin H.
357 55, H01L 2980, H01L 2906
Patent
active
044582595
ABSTRACT:
A gate-source structure and fabrication method for a static induction transistor. The method and the device are embodied by the epitaxial layer of, for example, high resistivity p-type semiconductor material grown on an epitaxial layer of high resistivity n-type semiconductor material. A silicon dioxide layer with source and gate windows is formed on the p-type epitaxial layer. Source grooves are formed in the p-type epitaxial layer at source window locations and the grooves are diffused with n-type impurities to form a diffusion region which extends to connect with the n-type epitaxial layer. Source and gate electrodes are formed in the source and gate windows.
REFERENCES:
patent: 3828230 (1974-08-01), Nishizawa et al.
patent: 4288800 (1981-09-01), Yoshida et al.
Edlow Martin H.
GTE Laboratories Incorporated
Lamont John
Lingren Theodore D.
Yeo J. Stephen
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