Etched back edge isolation process for heterojunction bipolar tr

Details Etched back edge isolation process for heterojunction bipolar tr Etched back edge isolation process for heterojunction bipolar tr

1989-04-10

1991-07-02

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 16, 437 67, 437 33, 437203, 437 31, 148DIG10, 148DIG100, 148DIG103, H01L 21265

Patent

active

050285491

ABSTRACT:
A method of isolating individual heterojunction bipolar transistors (HBTs) on a wafer increases the current gain which can be obtained when using proton implantation to isolate the transistor. The photoresist pattern which is used to cover the transistor location during isolation implantation is undercut when etching the cap layer. A dielectric is then deposited on the etched surface, including the undercut portion. The photoresist is lifted off and an HBT is fabricated on the wafer in the area which is not covered by the dielectric. The dielectric on the undercut portion confines the emitter current to a region slightly removed from the isolation implant and provides improved current gain.

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"Low Temperature Photo-CVD Oxide Processing for Semiconductor Device Applications," J. W. Peters; IEDM Processings, Washington, D.C. (1981)

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