Semiconductor device manufacturing: process – Chemical etching – Liquid phase etching
Reexamination Certificate
2000-01-18
2003-09-16
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Liquid phase etching
C438S747000, C438S750000, C438S753000
Reexamination Certificate
active
06620738
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an etchant for etching at least one of a titanium material and silicon oxide, which is mainly used in a semiconductor process; and a method for fabricating a semiconductor device using such an etchant. As used herein, the term “titanium material” refers to both titanium and titanium oxide.
2. Description of the Related Art
Recently, titanium materials have been a target of attention as materials for a semiconductor device. Specifically, titanium has become increasingly important as a metal material usable for interconnects of a semi-conductor circuit or for silicifying metal. Ceramic materials containing titanium oxide has a high dielectric constant and thus is used for memories and capacitors in GaAs high-frequency integrated circuits. Recently, integrated circuits including a capacitor formed of a material having a high dielectric constant such as, for example, BaSrTiO
3
or SrTiO
3
have been actively developed.
Conventionally, conventional titanium materials are generally etched by ion milling.
FIGS. 5A through 5E
show a method for processing a material for a capacitor having a high dielectric constant by ion milling.
As shown in
FIG. 5A
, a lower electrode layer
2
, a layer of a material used for a capacitor having a high dielectric constant (hereinafter, referred to as the “high dielectric constant capacitor material layer”)
3
, and an upper electrode layer
4
are sequentially formed on a substrate
1
. As shown in
FIG. 5B
, a resist mask
5
is formed on the upper electrode layer
4
. Then, as shown in
FIG. 5C
, the upper electrode layer
4
and the high dielectric constant capacitor material layer
3
are patterned by ion milling, thereby forming an upper electrode
4
a
. Standard conditions of ion milling include an accelerating voltage of 800 V and a beam current of 200 mA. Then, the resist mask
5
is removed. As shown in
FIG. 5D
, a resist mask
6
is formed on the lower electrode layer
2
so as to cover the high dielectric constant capacitor material layer
3
and the upper electrode
4
a
. The lower electrode layer
2
is patterned by ion milling as shown in
FIG. 5E
, thereby forming a lower electrode
2
a
. Then, the resist mask
6
is removed.
U.S. Pat. No. 4,759,823 discloses a two-step wet etching method used for PLZT. According to such a method, PLZT is immersed in a solution containing HCl and an F ion donor, and then immersed in nitric acid or acetic acid.
Ion milling which is performed for processing a titanium material can disadvantageously damage a semiconductor device due to Ar ions having a high energy. Ion milling has another problem of restricting the selection of the combination of the material to be milled and the material of an underlying layer. The wet etching method mentioned above also has the problem of significantly restricting the selection of the combination of the material to be etched and the material of an underlying layer formed of, for example, silicon oxide.
SUMMARY OF THE INVENTION
An etchant for etching at least one of a titanium material and silicon oxide includes a mixed liquid of HCl, NH
4
F and H
2
O.
In one embodiment of the invention, an etchant has a NH
4
F/HCl molar ratio of less than one.
In one embodiment of the invention, a method for fabricating a semiconductor device includes the step of etching a titanium material layer formed on a silicon oxide layer using such an etchant.
In one embodiment of the invention, an etchant has a NH
4
F/HCl molar ratio of more than one.
In one embodiment of the invention, a method for fabricating a semiconductor device includes the step of etching a silicon oxide layer formed on a titanium material layer using such an etchant.
In one embodiment of the invention, an etchant has a NH
4
F/HCl molar ratio of substantially one.
In one embodiment of the invention, a method for fabricating a semiconductor device includes the step of etching a lamination including a titanium material layer and a silicon oxide layer using such an etchant.
Thus, the invention described herein makes possible the advantages of providing an etchant for selectively etching either a titanium material or silicon oxide, or etching both a titanium material and silicon oxide at a substantially equal rate; and a method for fabricating a semiconductor device using such an etchant.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.
REFERENCES:
patent: 3777227 (1973-12-01), Krishma et al.
patent: 4759823 (1988-07-01), Asselanis et al.
patent: 5256247 (1993-10-01), Watanabe et al.
patent: 5350448 (1994-09-01), Dietz et al.
patent: 5402807 (1995-04-01), Moore et al.
patent: 5445979 (1995-08-01), Hirano
patent: 5587046 (1996-12-01), Stadler et al.
patent: 5828129 (1998-10-01), Roh
Ishida Hidetoshi
Noma Atsushi
Ueda Daisuke
Matsushita Electronics Corporation
RatnerPrestia
Utech Benjamin L.
Vinh Lan
LandOfFree
Etchant and method for fabricating a semiconductor device... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Etchant and method for fabricating a semiconductor device..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Etchant and method for fabricating a semiconductor device... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3074532