Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2000-12-11
2003-07-01
Chaudhuri, Olik (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S510000, C438S221000, C438S296000, C438S424000
Reexamination Certificate
active
06586814
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to semiconductor wafer processing. More particularly, the present invention relates to a new and improved way to form a shallow trench for isolating active components in an integrated circuit chip in a semiconductor wafer. Eroding or etching away of the shallow trench during subsequent processing is prevented, so the integrity of the shallow trench and the planarity of the semiconductor wafer are maintained.
BACKGROUND OF THE INVENTION
In the fabrication of integrated circuit (IC) chips on a semiconductor wafer, particularly for current advanced devices, it is often necessary to form shallow isolating trenches for insulation barriers between active components in the silicon of the IC to isolate the active components from each other and prevent electrical interference between the active components. Typically, a trench is formed between adjoining active areas to a predetermined depth in the silicon. The trench is filled with an insulating material, such as silicon oxide.
The silicon oxide (a.k.a. the oxide) is typically deposited across the wafer in either a chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD) process into the trench and onto the higher formations outside the trench. Then a chemical mechanical polishing (CMP) process is performed to remove the oxide from the formations outside the trench and to achieve a smooth uniform surface across the wafer. At this point, the isolating trench is completed, but exposed.
Various subsequent process steps typically use hydrofluoric acid (HF) or phosphoric acid to etch away or remove certain materials from the active areas. A certain amount of the exposed oxide in the trench, however, is usually also removed or eroded in these steps. In fact, deposited oxide typically etches at a faster rate than does thermally grown oxide, which is commonly formed in the active areas of the wafer outside the trench. The deposited oxide etches faster because it is typically not as dense as the thermally grown oxide. Additionally, if there has been an implant step (e.g. implanting nitrogen in portions of the wafer), then the deposited oxide may have been damaged by the implant step, and the damaged oxide will etch even faster. Therefore, the oxide in the trench typically etches away faster than the oxide outside the trench.
If too much of the oxide in the trench is etched away, then the planarity (e.g. smoothness or uniformity) of the surface of the wafer that was obtained through the CMP process may be lost. Proper planarity, however, is important for forming a pattern or image on the surface of the wafer, etching subsequent layers that are placed onto the wafer and other processing steps. Additionally, if silicon is deposited over the trench after a portion of the oxide in the trench has been eroded away, then a leakage pathway between active areas may accidentally be established over the trench. Therefore, HF and phosphoric acid etching steps and any other processing steps that may erode exposed portions of the oxide in the trench must be very rigorously controlled, so that an excessive amount of the oxide in the trench is not removed. Such rigorous control can be difficult to achieve.
It is with respect to these and other background considerations that the present invention has evolved.
SUMMARY OF THE INVENTION
The present invention prevents erosion or removal of the oxide in the shallow isolating trench between active areas of the semiconductor wafer by placing a layer of material, such as BTBAS (Bis-Tertiary-Butyl-Amino-Silane) nitride, which will not be substantially affected by the chemicals used in subsequent processing steps, onto the oxide in the trench. Since the etch rate of BTBAS nitride, or other appropriate etch resistant material, in HF or phosphoric acid is negligible, the processing steps that follow the placement of the BTBAS nitride over the oxide in the trench can be performed in a conventional manner without affecting the oxide in the trench.
These and other improvements are achieved by forming an isolating trench between active areas in a semiconductor substrate. A recess is formed for the isolating trench in the top of the substrate. Insulating material, such as a deposited oxide, is placed in the recess. An etch resistant material, preferably BTBAS nitride, is placed in a thin layer onto the insulating material in the recess. In this manner, the insulating material is protected from subsequent HF and phosphoric acid etch processes by the etch resistant material. Thus, when the substrate is exposed to such an etch substance, portions outside the isolating trench will be etched, while the etch resistant material and the insulating material will be left substantially intact.
To accomplish the process, the insulating material is preferably placed across the entire substrate, including inside the recess and outside the recess. A CMP step typically removes the insulating material from all regions outside the recess. Then an etch step preferably removes some of the insulating material from within the recess down to a predetermined height. The etch resistant material is then preferably placed across the entire substrate, including inside the recess on top of the reduced-height insulating material and outside the recess on top of the active areas. Another CMP step then removes the etch resistant material from regions outside the insulating material.
The previously mentioned and other improvements are also achieved in an improved isolating trench for electrically isolating adjacent active areas in a semiconductor substrate. The isolating trench includes a recess in the silicon substrate between the active areas, an insulating material disposed in the recess and an etch resistant material, preferably BTBAS nitride, overlaying the insulating material. The recess in the silicon substrate extends to a predetermined depth. The insulating material extends in the recess up to a predetermined height to form a primary electrically isolating portion of the isolating trench to prevent electrical interference between the active areas. Additionally, the insulating material is reactive with certain etch substances, such as HF and phosphoric acid. The etch resistant material, on the other hand, is unreactive with the same etch substances, so that the etch resistant material can protect the insulating material when the semiconductor substrate is exposed to the etch substances during the etching of portions of the active areas.
A more complete appreciation of the present invention and its scope, and the manner in which it achieves the above noted improvements, can be obtained by reference to the following detailed description of presently preferred embodiments of the invention taken in connection with the accompanying drawings, which are briefly summarized below, and the appended claims.
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Chan David
Gopinath Venkatesh P.
Kamath Arvind
Patel Rajiv
Rafftesaeth Ken
Chaudhuri Olik
Lee Hsien-Ming
Ley LLC John R.
LSI Logic Corporation
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