Etch aided by electrically shorting upper and lower sidewall...

Details Etch aided by electrically shorting upper and lower sidewall... Etch aided by electrically shorting upper and lower sidewall...

2006-08-22

2006-08-22

Chen, Kin-Chan (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S723000, C438S724000

Reexamination Certificate

active

07094699

ABSTRACT:
A method used to fabricate a semiconductor device comprises etching a dielectric which results in an undesirable charge buildup along a sidewall formed in the dielectric during the etch. The charge buildup along a top and a bottom of the sidewall can reduce the etch rate thereby resulting in excessive etch times and undesirable etch opening profiles. To remove the charge, a sacrificial conductive layer is formed which electrically shorts the upper and lower portions of the sidewall and eliminates the charge. In another embodiment, a gas is used to remove the charge. After removing the charge, the dielectric etch may continue. Various embodiments of the inventive process and in-process structures are described.

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