Estimation system of LSI power consumption

Details Estimation system of LSI power consumption Estimation system of LSI power consumption

1999-02-19

2001-11-20

Teska, Kevin J. (Department: 2123)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Circuit simulation

C703S018000, C716S030000

Reexamination Certificate

active

06321185

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to an estimation system of LSI (large scale integrated circuit) power consumption in order to make a rough estimate of power consumption and an internal power ratio of an LSI chip at the beginning stage of a system LSI designing.
DESCRIPTION OF THE RELATED ART
In the conventional estimation system of LSI power consumption, at the case estimating the power consumption of a new designing LSI chip, a power model of a basic cell and a logic block using loads and frequencies as parameters are provided in advance, the HDL (hardware description language) is applied, the estimation of a mapping for its own model (such as adder, mutiplexe, etc.) and the kinds of gates by the HDL are implemented. The frequency of every internal node is estimated by the frequency applied to the outside, the internal wiring load is estimated by a calculation equation and the power consumption of the LSI chip is made a rough estimate by the above mentioned power model.
The Japanese Patent Laid-Open Application No. HEI 7-73232 discloses the estimation system of LSI power consumption using the HDL. This system extracts the RTL (resistor transistor logic) part or the description of functions from the HDL and the power consumption is estimated by this extracted circuit information.
As mentioned above, at the conventional estimation system of the LSI power consumption, the HDL is applied for the estimation of the power consumption of LSI.
However, at the estimation system using the HDL, at the case that the result of the estimation is exceeded the expectations, the specifications and designing of the LSI chip have to be changed. With this change, the description of the HDL has to be largely modified or a new HDL has to be provided and the power consumption is estimated again. Therefore, the power consumption is estimated at the every time of the change of the specification and the description of the HDL, the final estimation of the power consumption is not obtained until the state that the designing is almost completed and the description of the HDL is arranged without the contradiction of logic.
Furthermore, at the above mentioned estimation system of the power consumption of LSI used the HDL, the logic block and the power model of the basic cell have to be completely provided as a library for this estimation. Therefore, a large man power is required to complete the logic block and the power model of the basic cell, however, there are many cases that the newest logic block has not been provided yet. Under this situation, when the power consumption is estimated and the result is beyond the expectation, it is very difficult to change largely the specification and the designing of the LSI chip. Even though the all logic blocks are provided, the power is not able to be completely described in each step of the logic block, therefore the value of the estimated power has a large error range.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide an estimation system of LSI power consumption which is able to obtain the power consumption of an LSI chip and the contents in high accuracy at the beginning stage of the designing without using the HDL.
According to a first aspect of the present invention, to solve the above mentioned problems, an estimation system of LSI power consumption, at which estimates the power consumption of a new designing LSI chip, provides an I/O (input/output) part estimating section which estimates I/O part power of an LSI chip based on the outside specifications required by the application of the LSI chip, and a modifiable circuitry part estimating section which is given voltage, frequency, the number of gates, unit capacity and clock structure and refers to the data base of kinds of functions and estimates the size of a clock tree and estimates a new designing part power of said new designing LSI chip.
According to a second aspect of the present invention, an estimation system of LSI power consumption, at which estimates the power consumption of a new designing LSI chip having core circuitry, provides an I/O part estimating section which estimates I/O part power of an LSI chip based on the outside specifications required by the application of the LSI chip, a core circuitry part estimating section which calculates the core power of an original LSI chip becoming the origin of the core circuitry subtracting the I/O part power of the existing original LSI chip from the known total power of the original LSI chip and converts voltage, process and frequency from the core power of the original LSI chip to the core circuitry power of the new designing LSI chip and estimates the core circuitry power of the new designing LSI chip and a modifiable circuitry part estimating section which is given voltage, frequency, the number of gates, unit capacity and clock structure and refers to the data base of kinds of functions and estimates the size of a clock tree and estimates a modifiable circuitry part power of said new designing LSI chip.
According to a third aspect of the present invention, an estimation system of LSI power consumption, at which estimates the power consumption of a new designing LSI chip, provides an I/O part estimating section which estimates I/O part power of an LSI chip based on the outside specifications required by the application of the LSI chip, a data base of the ratio of each function which stores the ratio of the number of FF (flip-flop)/gates and the ratio of clock power/logic power in the kinds of functions, a modifiable circuitry part estimating section which calculates the ratio of the number of FF/gates and the ratio of clock power/logic power referring to said data base of the ratio of each function from the kinds of functions and calculates clock system power based on the ratio of the number of FF/gates, voltage, frequency, the number of gates, unit capacity and clock structure and calculates logic system power using the ratio of the clock/logic power and calculates modifiable circuitry part power summing up the clock system power and the logic system power, and an LSI chip power calculating section which calculates the power of the new designing LSI chip summing up the I/O part power calculated at said I/O part estimating section and the new designing part power calculated at said new designing part estimating section.
According to a fourth aspect of the present invention, an estimation system of LSI power consumption, at which estimates the power consumption of a new designing LSI chip having core circuitry, provides an I/O part estimating section which estimates I/O part power of said new designing LSI chip and I/O part power of the existing original LSI chip having the core of the same function that the core circuitry of said new designing LSI chip has, based on the outside specifications required by the application of the LSI chip, a data base of the ratio of each function which stores the ratio of the number of FF/gates and the ratio of clock power/logic power in the kinds of functions, a core circuitry part estimating section which calculates the core power of the original LSI chip subtracting said I/O part power of the original LSI chip calculated at said I/O part estimating section from the known total power of the original LSI chip and converts voltage, process and frequency from the core power of the original LSI chip to the core circuitry power of the new designing LSI chip and estimates the core circuitry power of the new designing LSI chip, a new designing part estimating section which calculates the ratio of the number of FF/gates and the ratio of clock power/logic power referring to said data base of the ratio of each function from the kinds of functions and calculates clock system power based on the ratio of the number of FF/gates, voltage, frequency, the number of gates, unit capacity and clock structure and calculates logic system power using the ratio of the clock/logic power and calculates the modifiable circuitry part power summing up the clock system power and t

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