Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2001-11-07
2003-02-18
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S118000, C341S120000, C341S141000
Reexamination Certificate
active
06522282
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a parallel A/D converter having compensation for timing errors and in particular to estimating timing errors in a parallel A/D converter.
BACKGROUND
Many digital signal processing applications, such as mobile telephones or ADSL modems, require analog-to-digital (A/D) converters (ADCs) having very high sample rates. To achieve sufficiently high sample rates, an array of M A/D converters connected in parallel can be used. Each ADC should work at 1/Mth of the desired sample rate. To avoid time drift between the different ADCs, the same master clock is used for all ADCs, see the schematic layout of a parallel ADC in FIG.
1
. To get the same sample interval for all samples the nth ADC should be delayed by
nT
s
M
where T
s
is the sample interval for the master sampling clock, see Y-C Jenq, “Digital spectra of nonuniformly sampled signals: A robust sampling time offset estimation algorithm for ultra high-speed waveform digitizers using interleaving”, IEEE Transactions on Instrumentation and Measurement, 39(1), pp. 71-75, February 1990.
If errors exist in the delay times a non-uniformly sampled signal will be obtained. If these errors are not compensated, the resolution of the ADC will decrease by several bits, see the articles by S. K. Mitra A. Petraglia, “Analysis of mismatch effects among A/D converters in a time-interleaved waveform digitizer”, IEEE Transactions on Instrumentation and Measurement, 40(5), pp. 831-835, October 1991, Y-C Jenq, “Digital spectra of nonuniformly sampled signals: Fundamentals and high-speed waveformdigitizers,” IEEE Transactions on Instrumentation and Measurement, 37(2), pp. 245-251, June 1988, and Y-C Jenq, “Digital spectra of nonuniformly sampled signals: Digital look-up tunable sinusoidal oscillators,” IEEE Transactions on Instrumentation and Measurement, 37(3), pp. 358-362, September 1988.
However, if the delay errors are known, the true signal can be recovered, see L. Cuvelier. L. Vandendorpe, B. Maison, “RLS design of polyphase components for the interpolation of periodically nonuniformly sampled signals, in International Conference on Acoustics, Speech, and Signal Processing, 1995, Vol. 2, pp. 1229-1232, IEEE, and M. Ganshadzahi, F. Marvasti, M. Analoui, “Recovery of signals from nonuniform samples using iterative methods”, IEEE Transactions on Signal Processing, 39(4), pp. 872-878, April 1991. The errors are assumed to be static, so that.the error is the same in the same AD-converter from one cycle to the following one. Also, random errors in time and amplitude exist due to thermal noise, that are different from one sample to the next one. These errors are not associated with the special feature of the parallel structure of an A/D converter and are not discussed any further herein. In the diagram of
FIG. 2
a sine signal is shown that is converted using a parallel A/D converter, in which each elementary A/D converter has a fixed error in the sampling time that has been set at random. The timing errors are between 0 and 50 percent of the nominal sampling time. Some methods have been proposed to estimate these errors, see F. H. Irons D. M. Hummels, J. J. McDonald II, “Distortion compensation for time-interleaved analog to digital converters”, in IEEE Instrumentation an Measurement Technology Conference, 1996, pp. 728-731, IEEE June 1996, and U.S. Pat. No. 5,294,926 for J. J. Corcoran, “Timing and amplitude error estimation for time-interleaved analog-to-digital converters”, October 1992. However, these methods assume a known input signal.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a method of calculating values of timing offsets of the cells or elements of a parallel A/D converter for which the input signal is basically unknown.
Thus, in a method to be described hereinafter a calculating unit performs calculation of values of the timing offsets of the cells in a parallel A/D converter for a substantially unknown input signal. The method works without any calibration signal. The only. assumption made is that the energy spectrum of the input signal should be concentrated to lower frequencies. The timing offset estimation works well for signals bandlimited to about ⅓ of the Nyquist frequency. However, the accuracy of a parallel A/D converter using the method and compensating for the calculated timing offsets is still improved even if the bandwidth is at the Nyquist frequency. Noisy measurements can be handled by compensating for the noise variance, the noise variance being estimated before estimating the timing errors.
Generally, a parallel analog-to-digital converter device comprises a multitude of parallel converter cells sampling an input analog signal at successive times. These sampling times generally have timing errors. The output terminals of all of the cells are connected to a compensation device of some kind known in the art. The compensation device compensates the sampled values for the timing errors to provide corrected sampled values output from the parallell converter device. The converter device further comprises a calculating unit connected to the output terminals of the parallel cells and also to the compensation device. The calculating unit is arranged to calculate the timing errors by first calculating a sum of squared-differences of the sampled values from each pair of consecutive cells to obtain a difference of the timing offsets for the pair, the differences depending on said sum and on an average of the square of the first derivative of the input signal. Then the average of the squared derivative of the input signal is estimated from the sampled values from all cells. Estimated differences of the timing errors of each pair of consecutive cells are calculated to obtain the timing offset for each cell. The timing offsets are indicated with respect to the timing offset of a predetermined one of the parallel cells.
When calculating the estimated squared differences, the calculating unit can be arranged to approximate the input analog signal is at each sampling time by a first order series expansion involving a first derivative. In the estimation of the average the sum of the calculated sums of squared differences is advantageously calculated.
The calculating unit can also be arranged to calculate a variance of noise superposed on the sampled values and to correct the calculated sums for the variance. In the calculating of the variance the calculating unit can be arranged to first set each sampled value to be a linear combination of old sampled values and added thereto a noise term, thereafter estimating each sampled value as said linear combination of old sampled values, and finally minimizing the mean square error of the estimates of the sampled values to find estimates of coefficients in the linear combination. The determined minimized mean square error is then an estimate of the variance.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the methods, processes, instrumentalities and combinations particularly pointed out in the appended claims.
REFERENCES:
patent: 4763105 (1988-08-01), Jenq
patent: 4968988 (1990-11-01), Miki et al.
patent: 5294926 (1994-03-01), Corcoran
patent: 6081215 (2000-06-01), Kost et al.
A digital-background calibration technique for minimizing timing-error effects in time-interleaved ADCs; Huawen Jin; Lee, E.K.F.; Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transaction on, vol.: 47 Issue: 7, Jul. 2000; P. 603-.*
“Distortion compensation for time-interleaved analog to digital converters”; Hummels, D.M.; Mcdonald, J.J., II.; Irons, F.H.; IEEE, vol.: 1, 1996; pp.: 728-731 vol. 1.*
“Blind estimation of timing errors in interleaved AD converters”; Elbornsson, J.; Ekelund, J.-E. Acoustics, Speech, and Signal Processing, 2001. Proceedings. 2001 IEEE InternationalCo
Nguyen Khai M
Nixon & Vanderhye P.C.
Telefonaktiebolaget LM Ericsson (publ)
Tokar Michael
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