Semiconductor device manufacturing: process – Making device array and selectively interconnecting – With electrical circuit layout
Reexamination Certificate
2006-12-26
2006-12-26
Deo, Duy-Vu N (Department: 1765)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
With electrical circuit layout
C438S424000, C430S030000, C430S311000
Reexamination Certificate
active
07153728
ABSTRACT:
By making use of the remaining film thickness distribution (CMP pattern ratio) that is a distribution of estimates of the remaining film thickness after the CMP process, the first region A is abstracted from the patterning mask that corresponds to the region X where values of the remaining film thickness distribution is higher than the first threshold. Correction of the layout of the first dummy mask pattern (40a) is designed for forming the first dummy active region having a width no less than a predetermined width on the semiconductor outside the active region forming mask pattern (16) within the region A. In accompany with this patterning mask correction, correction of the insulation film removing mask pattern (40a′) is designed in the first region A′ of the insulation film removing mask so as to removed a predetermined area of the insulation film formed on the first dummy active region. Based on these designs, actual patterning and insulation film removing masks are formed.
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Deo Duy-Vu N
Oki Electric Industry Co. Ltd.
Takeuchi&Kubotera LLP
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