Estimation of pin-to-pin timing for compiled blocks

Details Estimation of pin-to-pin timing for compiled blocks Estimation of pin-to-pin timing for compiled blocks

1993-07-23

1997-01-21

Teska, Kevin J.

Boots, shoes, and leggings

364489, G06F 1750

Patent

active

055965059

ABSTRACT:
A method for producing an electrical circuit by determining the input-to-output timing of compiled circuit blocks includes steps of determining a signal delay of a component due to physical characteristics of the component. The physical characteristics include at least a capacitance based upon relative placement of the component during compilation of a circuit block. The method further includes steps of determining an input-to-output speed for a circuit block by combining delays due to physical characteristics through alternate paths of the circuit block, and producing a compiled circuit block having a plurality of components by placing the components in the circuit block based on the steps of determining.

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