Estimating digital frequency synthesizer jitter

Details Estimating digital frequency synthesizer jitter Estimating digital frequency synthesizer jitter

2011-01-04

2011-01-04

Liu, Shuwang (Department: 2611)

Pulse or digital communications

Testing

Phase error or phase jitter

C375S227000, C375S294000, C375S376000

Reexamination Certificate

active

07864834

ABSTRACT:
A method of estimating jitter for a DFS can include determining a plurality of linear equations, wherein each linear equation corresponds to, at least in part, a combination of multiplier and divisor attributes for setting an output frequency of the DFS, identifying maximum and minimum values for the slope component and the vertical axis intercept component from the plurality of linear equations, providing an equation for determining minimum jitter given, at least in part, an input frequency, and providing an equation for determining maximum jitter given, at least in part, an input frequency. A linear equation can be derived for estimating jitter of the DFS according to a specified input frequency and a specified value of the divisor attribute of the DFS. The linear equation further can depend upon the minimum jitter and the maximum jitter.

REFERENCES:
patent: 5889435 (1999-03-01), Smith et al.
patent: 6687629 (2004-02-01), Yamaguchi et al.
patent: 6795496 (2004-09-01), Soma et al.
patent: 2003/0125888 (2003-07-01), Yamaguchi et al.

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