Establishing internal control paths in ATM node

Multiplex communications – Pathfinding or routing – Switching a message which includes an address header

Reexamination Certificate

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Details

C370S395300, C370S396000, C370S398000

Reexamination Certificate

active

06480492

ABSTRACT:

BACKGROUND
1. Field of the Invention
The present invention pertains to the Asynchronous Transfer Mode (ATM), and particularly to establishing internal control paths in an ATM node.
2. Related Art and Other Considerations
The increasing interest for high band services such as multimedia applications, video on demand, video telephone, and teleconferencing has motivated development of the Broadband Integrated Service Digital Network (B-ISDN). B-ISDN is based on a technology know as Asynchronous Transfer Mode (ATM), and offers considerable extension of telecommunications capabilities.
ATM is a packet-oriented transfer mode which uses asynchronous time division multiplexing techniques. Packets are called cells and traditionally have a fixed size. A traditional ATM cell comprises 53 octets, five of which form a header and forty eight of which constitute a “payload” or information portion of the cell. The header of the ATM cell includes two quantities which are used to identify a connection in an ATM network over which the cell is to travel, particularly the VPI (Virtual Path Identifier) and VCI (Virtual Channel Identifier). In general, the virtual is a principal path defined between two switching nodes of the network; the virtual channel is one specific connection on the respective principal path.
At its termination points, an ATM network is connected to terminal equipment, e.g., ATM network users. Typically between ATM network termination points there are plural switching nodes, the switching nodes having ports which are connected together by physical transmission paths or links. Thus, in traveling from an originating terminal equipment to a destination terminal equipment, ATM cells forming a message may travel through several switching nodes.
A switching node has a plurality of ports, each of which can be connected by via a link circuit and a link to another node. The link circuit performs packaging of the cells according to the particular protocol in use on the link. A cell incoming to a switching node may enter the switching node at a first port and exit from a second port via a link circuit onto a link connected to another node. Each link can carry cells for plural connections, a connection being e.g., a transmission between a calling subscriber or party and a called subscriber or party.
The switching nodes each typically have several functional parts, a primary of which is a switch core. The switch core essentially functions like a cross-connect between ports of the switch. Paths internal to the switch core are selectively controlled so that particular ports of the switch are connected together to allow a message ultimately to travel from an ingress side of the switch to an egress side of the switch, and ultimately from the originating terminal equipment to the destination terminal equipment.
The coordination and control of an ATM switching node is accomplished by transmitting control cells over internal control paths established between processors of the node. It is an object of the present invention to provide a simplified approach for establishing internal control paths for an ATM node.
BRIEF SUMMARY OF THE INVENTION
To form internal control paths in an ATM node, “half trails” are initially established and subsequently connected to form complete trails. In an ATM node having plural node entities or device boards connected to a switch core, for each node entity a main control path program executed by a node main processor initially forms both a listening half trail and a sending half trail extending from the node main processor and switch core. Separately and independently, i.e., without prior communication with the node main processor, an entity control path program executed by an entity processor at each node entity establishes a listening half trail between itself and the switch core. For each node entity, the entity control path program establishes the same VPI/VCI (e.g., a predetermined VPI/VCI) as the listening half trail. The entity processor then receives on its independently established listening half trail a handshaking request. The handshaking request includes information indicating what half trail (e.g., what other VPI/VCI) the node entity can use as a sending half trail for sending cells to node main processor. The node entity then responds to the handshaking request with a response message sent over the sending half trail.
The same entity control path program is preferably loaded into each node entity. The entity control path program uses the same VPI/VCI to open a listening half trail at each node entity. The listening half trail can thus be set up without previous program interaction with the main control path program executed at the node main processor.
In one embodiment wherein the ATM node is a single stage node with a sole switch core, the half trails emanating from the node main processor are known as core-open half trails because they have one end terminated at the node main processor and another end open at the switch core of the node. In the single stage node embodiment, the handshaking request also includes an address of the node main processor on one of the node entities.
In another embodiment the ATM node is a multi-stage or cascaded node having plural switch cores, with each stage of the node having a node entity which serves as an extension terminal. A physical link connects the extension terminals of the two stages. The extension terminal of the second stage includes a VPI/VCI translation table and a traffic device. In the multi-stage node embodiment, the half trails emanating from the node main processor are known as interface-open half trails because they have a second end open to the physical link which connects the two stages of the node. In the multi-stage node embodiment, the handshaking request includes an address of the traffic device of a second stage switch which is to be used to forward cells to the node main processor.


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