Electricity: electrical systems and devices – Safety and protection of systems and devices – Circuit automatically reconnected only after the fault is...
Reexamination Certificate
2000-04-28
2002-07-23
Jackson, Stephen W. (Department: 2836)
Electricity: electrical systems and devices
Safety and protection of systems and devices
Circuit automatically reconnected only after the fault is...
C361S091100, C361S111000, C361S127000
Reexamination Certificate
active
06424510
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the design of integrated circuit (IC) products in the semiconductor industry and more particularly to an electrostatic discharge (ESD) structure having over-voltage capability at a pad during steady state.
ESD structures, or ESD protection circuits, are important because they divert harmful voltage or current surges, or ESD transients, from potentially vulnerable circuitry and pass such transients to ground (GND). To accommodate for such transients, it is desirable that the ESD structure adapt to operate at varying voltage ranges. This adaptation is important with the advent of low-power consumption products which are generally more vulnerable to ESD transients. For example, gate oxides from 0.35 um technology can generally withstand a maximum gate-to-drain or gate-to-source voltage of 3.6V. The maximum supply voltage (VDD) of ICs in 0.35 um technology is about 3.6V. There is great need for ICs that can tolerate pad voltages greater than VDD, e.g., 5V. Accordingly, if the pad can tolerate 5V, for example, the ESD structure should also tolerate 5V. When an NMOS structure of the prior art is used with ICs made with 0.35 um technology with a single gate-oxide thickness, a 5V input appearing at the pad in normal operation would cause the drain-to-gate voltage of the transistor to be 5V. In time, this would cause gate-oxide failure.
A need therefore remains for an ESD structure for ICs fabricated with sub-micron technology that can tolerate voltages at the I/O pin, or pad, higher than the voltage allowed for such technology. The design must also result in a significant reduction in fabrication costs and an increase in fabrication yield.
SUMMARY OF THE INVENTION
The present invention achieves the above needs and objectives with a new and improved ESD structure that can tolerate voltages at the I/O pin, or pad, higher than the voltage allowed for such technology. More particularly, the present invention provides an electrostatic discharge integrated circuit having a first and second NMOS transistor, a first and second voltage divider, a first and second steady state biasing circuit. The first NMOS transistor sinks electrostatic discharge current from an input/output pad to a ground source, the first NMOS transistor having a drain coupled to the input/output pad, and a gate. The first voltage divider has a node connected to the gate of the first NMOS transistor. The first steady state biasing circuit connects to the gate of the first NMOS transistor. The second NMOS transistor sinks electrostatic discharge current from the input/output pad to the ground source, the second NMOS transistor having a drain coupled to a source of the first NMOS transistor, and a source coupled to the ground source. The second voltage divider has a node connected to a gate of the second NMOS transistor. The second steady state biasing circuit connects to the gate of the second NMOS transistor.
In another embodiment the voltage dividers are capacitive, the voltage dividers having capacitors between the pad and ground, the bias of the voltage dividers being substantially at the mid-point.
In another embodiment, the first steady state biasing circuit ties the gate of the first NMOS transistor to a voltage source such that the drain-gate voltage of the first NMOS transistor remains within gate-oxide tolerance levels.
In another embodiment, the integrated circuit further has a shunting capacitor having a first node coupled to the drain of the second NMOS transistor and a second node coupled to the ground source.
The ESD structure of the present invention can tolerate voltages at the I/O pin, or pad, higher than the voltage allowed for such technology. Another advantage of this design is that the new ESD circuit requires only a single gate-oxide thickness giving significant reduction in fabrication cost and increase in fabrication yield.
The present invention achieves the above purposes and benefits in an inexpensive, uncomplicated, durable, versatile, and reliable circuit and method, inexpensive to manufacture, and readily suited to the widest possible utilization. The present invention achieves these purposes and benefits in the context of known circuit technology and known techniques in the electronic arts. Further understanding, however, of the nature, objects, features, and advantages of the present invention is realized by reference to the latter portions of the specification, accompanying drawings, and appended claims. Other objects, features, and advantages of the present invention will become apparent upon consideration of the following detailed description, accompanying drawings, and appended claims.
REFERENCES:
patent: 5576557 (1996-11-01), Ker et al.
Ajit Janardhanan S.
Le Hung Pham
Exar Corporation
Jackson Stephen W.
Townsend and Townsend / and Crew LLP
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