ESD resistant latch circuit

Details ESD resistant latch circuit ESD resistant latch circuit

1990-04-19

1990-12-18

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307572, 307303, 307289, H03K 1716, H03K 326

Patent

active

049788698

ABSTRACT:
A latch circuit which is resistant to electrostatic discharge includes four cross-coupled NOR gate pairs located in the four corners of an integrated circuit chip, and a fifth cross-coupled NOR gate pair positioned generally in the center of the integrated circuit chip. The Q outputs, the Q outputs, the reset inputs, and the set inputs of each of the five cross-coupled NOR gate pairs are connected together such that a single cross-coupled NOR gate pair receiving an electrostatic discharge will be held in its present state by the action of the other four cross coupled NOR gate pairs which will either supply current or sink current in order to maintain the state of the Q and Q-bar outputs.

REFERENCES:
patent: 3170071 (1965-02-01), Griesmer et al.
patent: 3860831 (1975-01-01), Goser
patent: 4213064 (1980-07-01), Nagano
patent: 4739378 (1988-04-01), Ferrari et al.
"Improved COS/MOS Inverter Circuit for Reducing Burn-Out and Latch-Up", RCA Technical Notes, Jul. 1979 by Andrew Dingwall.
"COS/MOS Electrostatic Discharge Protection Network" by Pujol, Electronic Technology, vol. 13, Feb. 1979.

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