Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means
Reexamination Certificate
2007-07-10
2007-07-10
Jackson, Stephen W. (Department: 2836)
Electricity: electrical systems and devices
Safety and protection of systems and devices
Load shunting by fault responsive means
C257S355000
Reexamination Certificate
active
11033395
ABSTRACT:
The invention relates to an ESD protection with ability to enhance trigger-on speed of a low voltage Triggered PNP (LVTPNP) unit for protecting internal circuits of an integrated circuit from attack of an ESD stress. The ESD protection unit incorporates either detection circuit or power clamp circuit to efficiently trigger on a trigger node as a heavily doped region of LVTPNP devices among an I/O pad, a VDD pin and a VSS pin. As soon as the trigger node of each LVTPNP device receives a trigger signal from either the ESD detection circuit or power clamp circuit, the threshold voltage of the LVTPNP devices are capable of being therefore reduced to enhance trigger-on speed of the LVTPNP devices that discharge ESD current.
REFERENCES:
patent: 5287241 (1994-02-01), Puar
patent: 5311391 (1994-05-01), Dungan
patent: 5530612 (1996-06-01), Maloney
patent: 5576557 (1996-11-01), Ker
patent: 5734541 (1998-03-01), Iniewski
patent: 5959820 (1999-09-01), Ker
patent: 5978192 (1999-11-01), Young
patent: 6002568 (1999-12-01), Ker
patent: 6011681 (2000-01-01), Ker
patent: 6249410 (2001-06-01), Ker et al.
patent: 6426855 (2002-07-01), Lee
patent: 6521952 (2003-02-01), Ker
patent: 6535368 (2003-03-01), Andresen
patent: 6549061 (2003-04-01), Voldman
patent: 6600198 (2003-07-01), Ohnakado et al.
patent: 6690557 (2004-02-01), Hung
patent: 6724603 (2004-04-01), Miller et al.
patent: 6765773 (2004-07-01), Reiner
patent: 2003/0075763 (2003-04-01), Ker et al.
patent: 2003/0076636 (2003-04-01), Ker et al.
patent: 2004/0085691 (2004-05-01), Ker
Ming-Dou Ker, Wei-jen Chang, Wen-Yu Lo. Low-Voltage-Triggered PNP Devices for ESD Protection Design in Mixed-Voltage I/O Interface with Over-VDD and Under-VSS Signal Levels. 2004. 0-7695-2093-6/04—IEEE (Computer Society). pp. 1-6.
Ker Ming-Dou
Lee Chein-Ming
Jackson Stephen W.
Roman Luis E.
Silicon Integrated System Corp.
Troxell Law Office PLLC
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