ESD protection system for high frequency applications

Details ESD protection system for high frequency applications ESD protection system for high frequency applications

2001-08-23

2004-10-05

Toatley, Jr., Gregory J (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

Reexamination Certificate

active

06801416

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to electrostatic discharge (ESD) protection circuits, and more particularly to ESD circuits for multiple power supplies in radio frequency (RF) applications.
2. Description of the Related Art
Integrated circuits, especially silicon integrated circuits (IC), are susceptible to damage caused by electrostatic discharge from environmental sources. Such sources of relative charge are human beings handling the wafer, die, or packaged IC, improperly grounded test and assembly equipment, and the device itself, which may accumulate charge during storage and transport. To avoid these post-fabrication yield losses, each IC must be designed to withstand the likely types of environmental electrostatic discharge it may face. The basic models used are the Human Body Model (HBM) as per
FIG. 1
, Machine Model (MM), and the Charged Device Model (CDM).
In
FIG. 1
a schematic for a Human Body Model (HBM) type ESD discharge tester is shown to the left of the dotted line. The 100 pF capacitor
11
and the 1.5 kOhm resistor
12
are essential to the model. The inductance
13
and other capacitances
14
and
15
are parasitic elements of the tester. The Device Under Test (DUT)
16
is shown to the right of the dotted line. In evaluation of the proposed ESD protection system, the inventors used the HBM in all of their testing.
Special devices are placed in the layout of the IC to steer the discharge current away from the functional IC circuitry. The scheme we have used in our implementation is based upon the prior art dual-diode and shunt scheme
200
shown in FIG.
2
. The diodes
204
,
205
connecting the I/O pads
202
to the power supply rails
206
,
207
(and the Vss to Vdd diode
208
) along with the power shunt
210
, which connects the power supply rails in the case of a positively ramped voltage from Vdd to Vss, provide a low impedance path for current flow between any two pins when the IC is powered down. For example, a positive spike from an I/O pad to Vss will cause current to run through a P+/N-well diode
204
and then down through the power shunt circuit
210
. The I/O circuits and core
214
receive their input directly from the I/O pads. The resistances
212
shown in the power supply rails are parasitic resistances that lead to voltage drops during the current pulse.
For the system to work properly, each current steering element (the diodes and the shunt) must drop as little voltage for as high a current as possible. Moreover, the parasitic metal resistances must be accounted for and understood. Therefore, the shunts and diodes must be well designed to be as efficient as possible.
RF circuits have an additional constraint that the diodes
204
,
205
on the input pads
202
must present very little capacitive loading to the signal compared with the amount that lower frequency parts can tolerate. In addition, this capacitance should preferably be bias-independent. The low-loading requirement dictates that the diodes must be scaled down, thus raising the voltage drop for a given ESD current. To compensate for this, the power shunt circuit must be designed to be very robust to allow for the greater drop from the I/O pad diodes
204
,
205
.
The diode-coupling and shunt scheme proposed by the inventors contrasts with those by Stackhouse et al. (U.S. Pat. No. 5,740,000), Worley et al. (U.S. Pat. No. 5,654,862), Maloney (U.S. Pat. No. 5,530,612), and Gens et al. (U.S. Pat. No. 5,515,225). The difference is that all of these use a single main shunt between two power supply nodes and couple other power supplies (including the Vdd supplies) via diodes or bridge circuits.
The clamp of the power shunt circuit differs from the one used by Stackhouse, et al. (U.S. Pat. No. 5,740,000) in the implementation of the RC timer. Prior art power shunt circuits are also shown by Miller et al. (U.S. Pat. No. 5,946,177) and Shay (U.S. Pat. No. 5,508,649) but differ in the implementation.
The proposed three-inversion RC-timed shunt for the power shunt circuit is superior to the one used by Ker (U.S. Pat. No. 5,744,842) and Strauss (U.S. Pat. No. 5,559,659) because of the advantage which PMOS devices provide and which will be shown in the body of the proposed invention.
Other U.S. Patents not already mentioned, but relating to the present invention, are:
U.S. Pat. No. 6,091,593 (Lin) discloses an RC timed ring-oscillator charge pump for inducing turn-on in MOS or bipolar protection devices.
U.S. Pat. No. 6,072,682 (Ravanelli et al.) describes an all NMOS RC-triggered source-follower shunt.
U.S. Pat. No. 6,014,298 (Yu) discloses an RC timed switch to be placed in series between power Vcc and circuit to be protected. The switch turns off when an ESD is detected to prevent discharge going through the core circuit.
U.S. Pat. No. 5,986,861 (Pontarollo) presents a simple clamp, with a PMOS final transistor and NMOS inverter triggered by RC.
U.S. Pat. No. 5,907,464 (Maloney et al.) describes a shunt circuit with a PMOS final driver and timed by a PMOS resistor/generic capacitor time constant.
U.S. Pat. No. 5,745,323 (English et al.) teaches an input line protection circuit which uses RC-timed PMOS and NMOS transistors to discharge ESD current to the Vdd and Vss power rails.
U.S. Pat. No. 5,287,241 (Puar) discloses a PMOS final driver triggered and timed by a PMOS resistor/NMOS capacitor RC.
U.S. Pat. No. 5,255,146 (Miller) describes an NMOS final driver with three RC timers, feedback loop, and NAND gate triggering to detect the rise time of the ESD, to insure that the ESD is longer than a typical noise pulse.
SUMMARY OF THE INVENTION
It is an object of the present invention to steer ESD currents away from the functional IC circuitry and thus protect this circuitry when an ESD is applied between any two pads of the IC in any direction, in particular with respect to RF IC circuitry.
It is another object of the present invention to provide this protection from ESD currents to circuits which utilize multiple power supply rails for both the more positive, Vdd, and the more negative, Vss, power supply rail.
It is yet another object of the present invention to provide complete isolation of the Vdd busses so that noise on one Vdd bus does not directly couple to another Vdd bus.
It is still another object of the present invention to provide this isolation with low capacitive loading for radio frequency (RF) systems.
It is a further object of the present invention to allow operation of the various Vdd busses at any supply voltage required for circuit operation.
It is yet a further object of the present invention to provide operation in which the various Vss busses may differ in potential by up to a single diode drop.
It is still a further object of the present invention to provide operation in which the various Vss busses are at the same potential and are joined together through the resistive substrate.
These and many other objects have been achieved by:
connecting together Vss busses by a pair of complementary polarity diodes made typically with P+/N-well diodes in an N/P-substrate process;
paying special attention to the I/O diodes of high frequency I/O pads, such that no resistance is in the signal path, and that the capacitance per diode is kept to less than 200 femto-Farads (200×10
−15
F);
special diode layout to insure that the highest current capacity per femto-Farad of loading capacitance is achieved;
insuring that the worst case ESD event will flow at most between two I/O pads and one power shunt;
insuring that the power shunt circuit clamps are at a very low voltage during an ESD event;
providing each pair of power rails its own shunt circuit thus placing each shunt in physical proximity to the I/O pad it must protect; and
providing an I/O diode layout with the largest perimeter/area ratio possible.
These and many other objects and advantages of the present invention will be readily apparent to one skilled in the art to which the invention pertains from a perusal of the claims, the appended drawings, and the foll

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