ESD protection scheme

Details ESD protection scheme ESD protection scheme

1995-06-23

1998-03-24

Gaffin, Jeffrey A.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

361111, H02H 900

Patent

active

057319405

ABSTRACT:
An apparatus and a method for providing ESD protection in integrated circuits is provided. The apparatus includes ESD protection circuits between interface pins and a substrate of the integrated circuit to discharge ESD current at one interface pin of the integrated circuit through the substrate to an ESD reference point at another interface pin. The ESD protection circuits include reverse breakdown devices that become conductive when a reverse breakdown threshold level is exceeded. The method includes discharging electrostatic charge from a first interface pin of the integrated circuit to a second interface pin through a substrate of the integrated circuit.

REFERENCES:
patent: 4829350 (1989-05-01), Miller
patent: 4839768 (1989-06-01), Daniele et al.
patent: 4855620 (1989-08-01), Duvvury et al.
patent: 4896243 (1990-01-01), Chatterjee et al.
patent: 5442217 (1995-08-01), Mimoto
patent: 5477414 (1995-12-01), Li et al.

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