Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means
Reexamination Certificate
2005-08-23
2005-08-23
Jackson, Stephen W. (Department: 2836)
Electricity: electrical systems and devices
Safety and protection of systems and devices
Load shunting by fault responsive means
C361S058000, C361S111000, C361S118000
Reexamination Certificate
active
06934136
ABSTRACT:
Electrostatic discharge protection devices formed at a face of a semiconductor substrate, integrated with a component sensitive to electrostatic discharge, wherein the protection device is interdigitated with the component.The invention is applicable to many kinds of components, for example to a noise-decoupling capacitor shaped as an nMOS transistor with thin dielectric, or to an input buffer shaped as an nMOS transistor, or to an antenna shaped as an nMOS transistor. The protection device includes an nMOS transistor. The insulator of the gates, preferably silicon dioxide, is thin and in need of protection against ESD damage.The interdigitation may be configured in one or more planes. Further, the protection device may lie in a single plane spaced apart from the plane defined by the components. The protection device may also partially be merged with the component.
REFERENCES:
patent: 5955763 (1999-09-01), Lin
patent: 6501136 (2002-12-01), Lin
patent: 6538300 (2003-03-01), Goldberger et al.
patent: 6661273 (2003-12-01), Lai et al.
Brady III W. James
Jackson Stephen W.
Telecky , Jr. Frederick J.
Texas Instrument Incorporated
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