Electricity: electrical systems and devices – Safety and protection of systems and devices – Transient responsive
Reexamination Certificate
1998-12-30
2001-07-24
Sherry, Michael J. (Department: 2836)
Electricity: electrical systems and devices
Safety and protection of systems and devices
Transient responsive
C361S056000, C257S362000
Reexamination Certificate
active
06266222
ABSTRACT:
TECHNICAL FIELD
This invention relates to an ESD (electrostatic discharge) protection network for circuit structures formed in a semiconductor.
More particularly, the invention relates to an ESD protection network for a CMOS circuit structure integrated in a semiconductor substrate and comprising discrete circuit blocks formed in respective substrate portions which are electrically isolated from one another and independently powered, respectively from at least one primary voltage supply having a respective primary ground, and from at least one secondary power supply having a respective secondary ground.
BACKGROUND OF THE INVENTION
As is well known, many VLSI (very large scale integration) electronic devices have ESD protection elements connected therein. These protection elements are connected directly to the pads of each device.
ESD protection elements are active during an electrostatic discharge to limit the resulting voltage surge and establish a low-resistance path toward the device ground.
Electrostatic discharges may concern any pad pairs, so that it becomes necessary to protect the electronic device by means of a “minimum protection network”. Such a network typically includes:
protective structures;
guard rings; and
bias diffusions for the substrate.
In this way, a low-impedance path would be ensured for any electrostatic discharge configurations.
In general, a protection network cannot be defined on the basis of quantitative estimates, because identifying discharge paths through components whose bias conditions are unknown is quite difficult.
Also difficult is to estimate the effectiveness of discharge paths which are dependent on the layouts of parasitic/active structures.
It should be further considered that the need to have circuit blocks or portions isolated may place constraints on the layouts which don't favor the creation of discharge paths.
These problems are felt more acutely with those devices which have separate discrete power supply lines.
For example, some memory devices include buffer output stages associated with their input/output (I/O) ports. These memory devices have a primary power supply for which Vcc and GND voltage supply references are usually provided. By contrast, their buffer output stages have a voltage supply Vcc_IO, GND_IO, referred to as the “secondary” supply hereinafter, which is separate and independent of the primary supply to the memory device.
The buffer stages generally consist of CMOS inverters comprising a PMOS pull-up transistor and an NMOS pull-down transistor.
The NMOS transistors of the buffer output stages are formed in a P-doped substrate which is biased to the secondary input/output ground, i.e., that denoted by GND_IO. The PMOS transistors are instead formed within an N-well biased to the secondary power supply Vcc_IO. On the other hand, the buffer input stages are formed in a ground biased native P substrate.
Now, the need to provide ESD protection for the CMOS circuitry of both supplies involves the use of respective protection elements biased by the two grounds GND, GND_IO in the same substrate. This, however, introduces a noise propagation line.
The presence of noise in CMOS devices may cause overshooting on the supply lines Vcc, GND, the overshoot being produced by fast switching of the buffer output stages of the input/output ports.
With the requirement for immunity to noise also to be met, conventional protection networks are unsuitable for use in a device as just described.
Even if an attempt were made at maintaining the connections to the substrate through the internal circuitry ground GND alone, the protection elements of the input/output circuitry toward the secondary ground GND_IO would introduce a diode wherethrough noise can be passed anyway. The noise intensity, in fact, lies well above the threshold of the forward-biased diode.
SUMMARY OF THE INVENTION
An embodiment of this invention provides an ESD protection network for VLSI electronic devices incorporating circuit blocks which are formed discretely in respective substrate portions isolated electrically from one another and powered independently.
The ESD protection network has such constructional and functional features as to be immune to substrate noise, and accordingly, allow the different circuit blocks to be isolated from noise or disturbance.
The ESD protection network provides, on the occurrence of an ESD discharge, a low-impedance path between any pair of pads of the integrated circuit structure.
The features and advantages of a protection network according to the invention will be apparent from the following description of an embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings.
REFERENCES:
patent: 5034845 (1991-07-01), Murakami
patent: 5159426 (1992-10-01), Harrington, III
patent: 5416351 (1995-05-01), Ito et al.
patent: 5506742 (1996-04-01), Marum
patent: 5521789 (1996-05-01), Ohannes et al.
patent: 5530612 (1996-06-01), Maloney
patent: 5623156 (1997-04-01), Watt
patent: 5629545 (1997-05-01), Leach
patent: 5905288 (1999-05-01), Ker
patent: 5991135 (1999-11-01), Saleh
patent: 0782192 (1997-07-01), None
Annunziata Roberto
Campardo Giovanni
Colombo Paolo
Maccarrone Marco
Mulatti Jacopo
Galanthay Theodore E.
Huynh Kim
Iannucci Robert
Seed IP Law Group PLLC
Sherry Michael J.
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