ESD protection for SOI circuits

Details ESD protection for SOI circuits ESD protection for SOI circuits

1988-05-26

1991-01-29

James, Andrew J.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

357 238, 357 2313, 357 42, 357 57, 357 59, 307283, H01L 2701, H01L 2713, H01L 2978

Patent

active

049890573

ABSTRACT:
A floating body field effect transistor having a defined breakdown voltage, and a lower holding voltage, serves to clamp electrostatic discharge voltages to a low voltage level, thereby minimizing thermal power dissipation within the thin semiconductor layer of semiconductor-on-insulator circuits.

REFERENCES:
patent: 4489339 (1984-12-01), Uchida
patent: 4763183 (1988-08-01), Ng et al.
Schwob, P., SOS Technology, Bull. ASE/UCS 68 (1972) pp. 60-65.
"C-MOS/SOS Gate-Protection Networks", R. K. Pancholy and T. J. Oki, IEEE Transactions on Electron Devices, vol. ED-25, p. 927, 1978.
"An Improved Input Protection Circuit for C-MOS/SOS Arrays", S. H. Cohen and G. K. Caswell, ibid, p. 926.
"C-MOS/SOS LSI Input/Output Protection Networks", B. T. Ahlport, J. R. Cricchi and D. A. Barth, ibid, p. 933.
"Design and Characterization of Input Protection Networks for CMOS/SOS Application", W. Palumbo and M. P. Dugan, EOS/ESD Symposium Proceedings, p. 182, 1986.

Affiliated with

Also associated with

Rating

ESD protection for SOI circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with ESD protection for SOI circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and ESD protection for SOI circuits will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-817648