ESD protection for high voltage level input for analog applicati

Details ESD protection for high voltage level input for analog applicati ESD protection for high voltage level input for analog applicati

1997-10-17

1999-12-14

Gaffin, Jeffrey

Electricity: electrical systems and devices

Safety and protection of systems and devices

Transient responsive

361 56, H02H 322

Patent

active

060025670

ABSTRACT:
The present invention provides for ESD protection while allowing the use of an input signal that is higher than V.sub.DD. The present invention preferably includes a protection device and a delay circuit coupled to an input pad and to a ground reference. The protection device is a preferred silicon controlled rectifier, and the delay circuit is preferably a low pass filter RC circuit that includes a resistor and a capacitor. A node associated with the delay circuit is coupled to circuitry of an integrated circuit. The circuitry has associated therewith at least one gate oxide breakdown voltage. A gate oxide breakdown voltage is prevented from being applied to the circuitry of the integrated circuit. When an ESD voltage is applied to the input pad, the voltage at that pad ramps or increases quickly. The delay circuit prevents the node from ramping as quickly by delaying the ramping or increasing of the node voltage. This delay provides time for the protection device to turn on and sink the ESD current.

REFERENCES:
patent: 4890187 (1989-12-01), Tailliet et al.
patent: 5430602 (1995-07-01), Chin et al.
patent: 5463239 (1995-10-01), Muhlemann
patent: 5502328 (1996-03-01), Chen et al.
patent: 5517051 (1996-05-01), Chatterjee
patent: 5528188 (1996-06-01), Au et al.
patent: 5652455 (1997-07-01), Zambrano
patent: 5686751 (1997-11-01), Wu

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