ESD protection for field effect transistors of analog input...

Details ESD protection for field effect transistors of analog input... ESD protection for field effect transistors of analog input...

2011-08-16

2011-08-16

Patel, Dharti H (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C361S118000

Reexamination Certificate

active

08000068

ABSTRACT:
During an ESD event, an ESD current flows from a ground node of a first ESD protection circuit and out of an integrated circuit to a terminal of a package that houses the integrated circuit. To improve ESD performance, a second ESD protection circuit is provided. A diode of the second ESD protection circuit is coupled between the ground node and the body of an input transistor of a Low Noise Amplifier (LNA). If the voltage on the ground node changes quickly during an ESD event (for example, due to a current spike flowing across a wire bond), then the diode charges the body of the transistor, thereby preventing a large gate-to-body voltage from developing across transistor. In some embodiments, another ground bond pad is provided and the second ESD protection circuit includes other diodes that charge or discharge other nodes during the ESD event to prevent transistor damage.

REFERENCES:
patent: 6501632 (2002-12-01), Avery et al.
patent: 7110228 (2006-09-01), Chang
patent: 7649722 (2010-01-01), Thijs et al.
patent: 2004/0190209 (2004-09-01), Jozwiak et al.
patent: 0623958 (1994-11-01), None
patent: 0736904 (1996-10-01), None
International Search Report and Written Opinion—PCT/US2009/062254, International Search Authority—European Patent Office—Feb. 9, 2010.

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