ESD protection for deep submicron CMOS devices with minimum trad

Details ESD protection for deep submicron CMOS devices with minimum trad ESD protection for deep submicron CMOS devices with minimum trad

1995-11-13

1998-02-17

Gaffin, Jeffrey A.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

361111, 257173, 257356, H02H 322, H01L 2362

Patent

active

057197334

ABSTRACT:
Apparatus and process for making the apparatus for electrostatic discharge (ESD) protection of an electronic device, using a silicon controlled rectifier (SCR) configuration. A spaced apart p-well and n-well are formed in a substrate, and spaced apart p+ and n+ contact regions are formed in each well, with an additional n+ or p+ drain tap contiguous to and lying between the two wells. The wells may be formed by a retrograde process or by a conventional process, with or without an epitaxial layer. A first electrode (ground) is connected to the p+ and n+ contact regions and through a polysilicon region to a gate oxide region in the first well. The polysilicon region has a small, controlled poly length. A second electrode is connected to the p+ and n+ contact regions in the second well and to an electrical circuit to be protected against ESD. The second well may be replaced by a portion of the substrate, of opposite electrical polarity to the first well. The triggering voltage for snapback of the SCR device is tunable over a voltage range as low as 5-11 Volts, and the device dynamical resistance in the on-state is about 8-9 Ohms. The SCR device has reduced tradeoff with latchup behavior of the electronic device to be protected.

REFERENCES:
patent: 5140401 (1992-08-01), Ker et al.
patent: 5343053 (1994-08-01), Avery
patent: 5400202 (1995-03-01), Metz et al.
patent: 5430595 (1995-07-01), Wagner et al.

Affiliated with

Also associated with

Rating

ESD protection for deep submicron CMOS devices with minimum trad does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with ESD protection for deep submicron CMOS devices with minimum trad, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and ESD protection for deep submicron CMOS devices with minimum trad will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1788653