ESD protection for bipolar-CMOS-DMOS integrated circuit devices

Details ESD protection for bipolar-CMOS-DMOS integrated circuit devices ESD protection for bipolar-CMOS-DMOS integrated circuit devices

2008-09-30

2010-06-15

Jackson, Stephen W (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

Reexamination Certificate

active

07738224

ABSTRACT:
An Electro-Static Discharge (ESD) protection device is formed in an isolated region of a semiconductor substrate. The ESD protection device may be in the form of a MOS or bipolar transistor or a diode. The isolation structure may include a deep implanted floor layer and one or more implanted wells that laterally surround the isolated region. The isolation structure and ESD protection devices are fabricated using a modular process that includes virtually no thermal processing. Since the ESD device is isolated, two or more ESD devices may be electrically “stacked” on one another such that the trigger voltages of the devices are added together to achieve a higher effective trigger voltage.

REFERENCES:
patent: 4683483 (1987-07-01), Burnham et al.
patent: 2002/0130390 (2002-09-01), Ker et al.
patent: 2005/0133873 (2005-06-01), Li et al.
patent: 2005/0205937 (2005-09-01), Wang
patent: 2008/0029820 (2008-02-01), Disney et al.
patent: 2009/0032876 (2009-02-01), Disney et al.
patent: 2009/0034137 (2009-02-01), Disney et al.

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