ESD protection for a CMOS output stage

Details ESD protection for a CMOS output stage ESD protection for a CMOS output stage

2002-08-16

2004-07-20

Jackson, Stephen W. (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

Reexamination Certificate

active

06765773

ABSTRACT:

The invention relates to an arrangement for improving the ESD protection in an integrated circuit.
In integrated circuits CMOS output driver stages or CMOS buffers are used to provide a corresponding amplification of a signal to be output by the integrated circuit. They are used, for example, in display devices in activation or driver circuits.
Electrostatic discharges (ESD) are one of the most destructive, unavoidable environmental influences to which electronic systems and integrated circuits are exposed. For example, in the event of ESD, integrated circuits must conduct currents in the order of several amps within a few nanoseconds. The destructive influence of these current densities on the circuit lies, on the one hand, in the very high thermal power dissipation in relation to the size of the circuit element, whilst on the other hand overvoltages which can destroy thin oxides are generated on the chip. From the point of view of circuit development in modern VLSI processes, overcoming these parasitic effects is becoming the central problem, since miniaturization increases the sensitivity to ESDs.
Electrostatic charges are produced by friction between materials, as can be caused by walking on carpets. Build-up and storage of the charge can lead to electrostatic potentials of several kV. When they come into contact with highly integrated semiconductor components these stored charges are discharged, a phenomenon also referred to as electrostatic discharge (ESD). From an electrical standpoint, electrostatic discharges represent transient high-current events with a peak current of several amps, lasting from 10 ns to 300 ns. These transient currents are a threat to integrated circuits in various ways:
on the one hand, the electrical overloads can destroy the integrated circuit due to overheating,
on the other hand, an overvoltage can cause gate oxide breakdowns in the MOS gates,
in addition, repeated ESD loads can give rise to degradation phenomena, which lead to an increase in the leakage currents.
Regardless of the type of ESD load, the semiconductor component or the integrated circuit either sustains irreparable damage or its capacity to function becomes deficient or deteriorates.
With increasing integration density of CMOS processes, there is also an increased risk of failures in integrated circuits that can be attributed to destruction by electrostatic discharges.
Known ESD protection circuits are designed to limit the voltage, The actual circuit to be protected must have a corresponding resistance to overvoltages.
With ever-increasing miniaturization of integrated circuits it is also particularly necessary to make effective use of the available chip area.
WO 0048252 describes an arrangement in which components are arranged under the bonding pad. These are arranged, in particular, under the edge of the bonding pad, since the least damage due to mechanical stress occurs there. These components are formed by differently doped layers, so that under the bonding pad there are areas which have different electrical potentials. If the bonding pad is damaged, short-circuits between these different potentials can impair the functionality of the circuit.
Locating components under the bonding pads of the CMOS circuit carries the disadvantage that the connection of the bonding pad to the terminals of a circuit package or lead frame by means of bonding, for example, exerts a mechanical stress on the bonding pad, so that the layers situated under the bonding pad, including active components, may be destroyed, with the result that the functionality of the integrated circuit is not assured.
Therefore, it is an object of the invention to provide an arrangement which permits an effective utilization of the chip surface area with improved ESD protection of the integrated circuit, and which ensures that the functionality of the integrated circuit is not impaired in the event of mechanical stressing of a bonding pad.
According to the invention this object is achieved by an arrangement for improving the ESD protection in an integrated circuit, in which a passive component, which is arranged under a bonding pad and over a non-conductive layer, is connected between the bonding pad and the integrated circuit.
In order to afford CMOS circuits adequate ESD protection, very large resistors are usually necessary, which take up a lot of space on the chip surface. A typical output stage of a CMOS circuit comprises at least one bonding pad, one PMOS transistor and one NMOS transistor, which are both connected in such a way that they form an output driver stage. In addition, an ESD protection circuit is generally also connected. A number of diodes can also be connected to the various potentials.
The ESD protection circuit limits the voltage in the event of an ESD. Owing to the snapback phenomenon, the NMOS transistor of the output driver stage is particularly at risk of being destroyed by the large current flowing in the event of an ESD. Further measures are needed in order to limit this current. One known method of doing this is to connect a resistor in series with the NMOS transistor, thereby limiting the current. Since this resistor should have a sufficiently high resistance to current, however, it needs to be correspondingly large. In highly miniaturized circuits, however, space on the actual chip surface is extremely limited. For this reason it is proposed to locate a passive component under the bonding pad for the additional protection of the NMOS transistor.
A connecting wire is bonded to the bonding pad. This wire connects the corresponding bonding pad of the integrated circuit to the terminal on the package/lead frame of the integrated circuit. Compared to the ESD protection circuit or the output driver circuit, the bonding pad takes up the most space in the output stage. During testing of the circuit, the bonding pad is exposed to mechanical stress by test needles. The bonding process also subjects the bonding pad to a high mechanical stress, due to the contact pressure required and the ultrasonic cold welding of the metal of the bonding ball to that of the bonding pad. As a result cracks can occur in the underlying layers, which cracks affect the functionality within these layers due to leakage currents, short-circuits or breaks, for example. For this reason, components have hitherto not been located directly under the bonding pads, or only where there was readiness to accept reduced reliability.
According to the invention, a passive component, which is connected between the NMOS transistor and the bonding pad, is located under the bonding pad. The bonding pad is formed by several metal layers, which are connected by electrically conductive connectors or VIAs. These VIAs also have a mechanical stabilizing effect when the bonding pad is subjected to load stresses. According to the invention, a passive component, one terminal of which is connected to the bonding pad by way of a VIA, is arranged under these metal layers. Connected to the other terminal of the passive component is the integrated circuit, in particular the output driver stage. This ensures that in the event of an ESD a high current flow is limited by means of the passive component. Arranging the passive component under the metal layers means that, if the metal layers are destroyed or damaged by mechanical pressure acting on the bonding pad, at worst only leakage current paths are created which bridge the passive component in that, for example, an insulating layer develops cracks through which metal could be pressed, thereby bridging the passive component. This leakage current path, however, does not affect the functionality of the ESD protection circuit, the output driver circuit or the integrated circuit. For this purpose preferably only the passive component is arranged under the bonding pad; moreover, it is arranged on an electrically non-conductive layer, so that in the event of damage and any short-circuit, no further components can be short-circuited, thus impairing the functionality.
In a preferred embodiment it is proposed to

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