ESD protection element

Details ESD protection element ESD protection element

2002-09-30

2004-09-14

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Regenerative type switching device

Device protection

C257S107000, C257S174000

Reexamination Certificate

active

06791123

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an electrostatic surge protection element for protecting a semiconductor device against surge due to electrostatic discharge (ESD).
2. Description of the Prior Art
ESD tends to destroy or damage a semiconductor device and is an importance factor substantially influencing reliability of the semiconductor device. As shown in
FIG. 1
, it has been usual in order to protect a semiconductor device
1
against ESD to provide a voltage regulator diode (Zener diode)
2
designed to operate at a predetermined voltage or higher on an input side of the semiconductor device
1
.
A general voltage regulator diode used as the ESD protection element will be described with reference to FIG.
2
. In
FIG. 2
, a high impurity density p
+
type guard ring region
4
and a p
+
type region
5
surrounded by the guard ring region
4
are selectively formed in a surface layer on a main surface (on a surface side) of an n
+
type silicon substrate
3
, which is a high impurity density n type semiconductor substrate, by injecting or diffusing boron ion as impurity. On the surface of the silicon substrate
3
, a silicon oxide film
6
is formed. A metal anode electrode
7
connected to a terminal A is electrically in contact with a surface of the p
+
region
5
, which is defined by an opening portion of the silicon oxide film
6
. Further, a metal cathode electrode
8
connected to a terminal K is electrically in contact with the other main surface of the silicon substrate
3
.
The guard ring
4
and the p
+
region
5
, which are formed between the anode electrode
7
and the cathode electrode
8
, and the n
+
type silicon substrate
3
forms a single PN junction J
1
. The PN junction J
1
has a parasitic capacitance C
1
, which is proportional to a junction area thereof.
Besides, in order to satisfy the recent requests of higher speed, that is, higher frequency of an input signal to a semiconductor device, it is necessary to reduce the parasitic capacitance C
1
of the voltage regulator diode. However, when the parasitic capacitance C
1
is reduced by reducing the junction area of the PN junction J
1
, durability of the PN junction against ESD, which is in a trade-off relation to the junction area, is degraded.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an ESD protection element for protecting a semiconductor device against electrostatic surge, whose parasitic capacitance can be reduced without reducing a junction area thereof.
An ESD protection element for protecting a semiconductor against electrostatic surge, according to a first aspect of the present invention, includes a high impurity density n type semiconductor substrate having low impurity density layer of one conductivity type (for example, n type) formed epitaxially on one of main surfaces thereof and an anode electrode electrically in contact with the other main surface thereof. A region of the other conductivity type (p type) is selectively formed in a surface layer of the low impurity density n type layer. A high impurity density n type region is formed selectively in a surface layer of the p type region and a cathode electrode is electrically in contact with, a surface thereof.
An ESD protection element for protecting a semiconductor against electrostatic surge, according to a second aspect of the present invention, includes a high impurity density n type semiconductor substrate having low impurity density layer of n conductivity type formed epitaxially on one of main surfaces thereof and an anode electrode electrically in contact with the other main surface thereof. A p type region is selectively formed in a surface layer of the low impurity density n type layer. A first high impurity density n type region is formed selectively in a surface layer of the p type region and having a cathode electrode electrically in contact with a surface thereof. And a second high impurity density n type region is formed simultaneously with the formation of the first high impurity density n type region such that it extends over the surface layer of the low impurity density n type layer and a surface layer of the p type region.
In this ESD protection element, the second high impurity density n type region is preferably formed by non-continuous regions arranged in a line surrounding the first high impurity density n type region.


REFERENCES:
patent: 5372957 (1994-12-01), Liang et al.
patent: 5821586 (1998-10-01), Yamaguchi et al.
patent: 5903028 (1999-05-01), Quoirin et al.
patent: 6060763 (2000-05-01), Yamagishi et al.
patent: 406291337 (1994-10-01), None
S. Wolf and R.N. Tauber, “Silicon Processing in the VLSI Era, vol. 1—Process Technology”, Second Edition, pp. 234-235; Lattice Press, Sunset Beach, California (2000) (ISBN 0-09616721-6-1).

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