ESD protection devices for a differential pair of transistors

Details ESD protection devices for a differential pair of transistors ESD protection devices for a differential pair of transistors

2001-08-02

2004-02-17

Han, Jessica (Department: 2838)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C330S261000, C330S296000

Reexamination Certificate

active

06693780

ABSTRACT:

BACKGROUND OF THE INVENTION
The invention generally relates to electronic protection devices, and more particularly to electrostatic discharge (ESD) protection devices for a differential pair of transistors.
Integrated circuits are susceptible to a variety of reliability problems. One of these issues is the possible vulnerability to ESD events. ESD occurs when a charged object, e.g., a piece of equipment used to install integrated circuits into a printed circuit board, is brought into close proximity to a pin of an integrated circuit that is at a different potential compared to the charged object. The discharge consists, typically, of current levels exceeding an ampere during a time period less than 200 nanoseconds. The magnitude of the peak current and the wave shape of the discharge depend on the effective resistance, capacitance and inductance of the system and the amount of charge present before the discharge. The result of ESD on unprotected integrated circuits is often destruction characterized by melting and/or explosion of part of the circuit. It is common practice for the designer to include extra components in an integrated circuit that are intended to provide protection against ESD damage by providing paths for the ESD events that bypass the components used for the normal circuit functions and are not destroyed by the ESD events.
In BiCMOS integrated circuits, a frequently used circuit configuration is a differential pair
10
of bipolar transistors, as shown in FIG.
1
. When this configuration is used as an input with the bases of the transistors connected to external bonding pads, it is very difficult to protect these transistors from ESD events.
A typical ESD protection scheme is shown in FIG.
2
. If pad A is stressed positive with respect to pad B, one of the likely paths for the ESD current is through a resistor R
1
, the forward biased base-emitter junction BE-
1
, the reverse biased base-emitter junction BE-
2
, and a resistor R
2
. In high frequency integrated circuits, transistors Q
1
and Q
2
are small in area, significantly limiting the ability of the base-emitter junction to carry current in the forward direction before the internal power dissipation is sufficient to cause damage. The base-emitter junction is very weak in the reverse direction, with a typical breakdown voltage of 4 V or less. Resistors R
1
and R
2
are often low-valued resistors to improve performance. The result of this configuration is that it is very difficult to protect the differential pair against the effects of ESD events.
The ESD protection scheme shown in
FIG. 2
is required to limit the voltage between points C and D to a safe value during a typical ESD event, where the discharge current may exceed 2 A. For high forward currents, the internal series resistance of the diode results in a larger forward drop (typically 2 to 3 V) than the typical low current diode drop (0.7 V). The preferred current path would be through diode D
1
, a power supply clamp
12
, and diode D
4
. If it is assumed that the voltage drop across power supply clamp
12
is 5 V, and the voltage across each of the two diodes in forward bias under the ESD event is 3 V, then 11 V appears from pad A to pad B. Also, if it is assumed that the current through the reverse biased BE-
2
is limited to 10 &mgr;A with a voltage drop of 4 V and that the voltage drop across the forward biased BE-
1
is 0.6 V at 10 &mgr;A, then the voltage drop across resistor R
1
plus resistor R
2
must be 6.4 V at 10 &mgr;A. The result is that R
1
and R
2
, which are equal, must be at least 320 k&OHgr; to protect the device. For high performance, it may be necessary to limit R
1
and R
2
to less than 100&OHgr; each. Note that it may be necessary to limit the current through the reverse biased base-emitter junctions to 1 &mgr;A or less for very small devices. An alternative is to increase the physical size of the transistors, which degrades the performance, to improve ESD protection.
An alternative approach is to divert the current from the input pads A and B directly. One such approach is shown in
FIG. 3
, where anti-parallel diodes, D
5
and D
6
, are connected between pads A and B. This approach limits the voltage across the differential pair to one high current diode drop (approximately 3 V), if the same assumptions as in the above for
FIG. 2
are used. Note that the other diodes are also necessary to provide protection for ESD stresses from the pads to the power supply and ground. The major difficulty with this approach is that the input signal current is also partially diverted by the diode pair D
5
and D
6
, limiting the input voltage swing to approximately 0.6 V in either polarity. If the input swing is larger than 0.6 V, the anti-parallel diodes D
5
and D
6
are no longer a valid solution for ESD protection.
Therefore, there is a need for an effective ESD protection scheme that allows a larger input voltage swing.
SUMMARY OF THE INVENTION
The invention provides a way of protecting a differential pair of transistors by providing a current path between input terminals of the transistors, while limiting the voltage across reversed biased junctions of the transistors. The invention also allows a larger input voltage swing at the input terminals of the transistors.
According to the present invention, an electrostatic discharge protection circuit is provided for protecting a differential pair of transistors. Each transistor includes first and second terminals and an input terminal. The second terminals of the transistors are connected to each other. The circuit comprises a pair of bypassing circuits and a clamping circuit. Each bypassing circuit is connected in parallel with a junction formed by the input and second terminals of an associated one of the transistors to limit a voltage across the junction when the junction is reverse biased. The clamping circuit is connected in parallel with the two input terminals of the transistors for setting an allowed differential voltage swing between the input terminals to a predetermined level.
According to one embodiment of the invention, the clamping circuit is connected between the input terminals of the transistors.
According to another embodiment of the invention, the clamping circuit is connected between two external pads which are respectively connected to the input terminals of the transistors.
In a specific embodiment of the invention, the clamping circuit includes a set of anti-parallel diodes and each bypass circuit includes a diode that is connected in parallel with the junction of the associated transistor.
Other objects and attainments together with a fuller understanding of the invention will become apparent and appreciated by referring to the following description and claims taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 4206418 (1980-06-01), Dingwall
patent: 4390812 (1983-06-01), Seidler
patent: 4717888 (1988-01-01), Vinn et al.
patent: 5311083 (1994-05-01), Wanlass
patent: 0388896 (1990-09-01), None

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