ESD protection device using static capacitance coupling between

Details ESD protection device using static capacitance coupling between ESD protection device using static capacitance coupling between

1996-08-23

1998-02-10

Gaffin, Jeffrey A.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

361111, H02H 900

Patent

active

057175608

ABSTRACT:
A method and an apparatus protecting an integrated circuit from electrostatic discharge. In one embodiment, a method of coupling the gate of an ESD protection transistor high during an ESD event to ensure a more efficient protection device is described. The method uses static fixed parallel plate capacitances coupled to the gate of an ESD protection device to place the ESD protection device above threshold during an ESD event. The fixed parallel plate capacitances form capacitors between the gate-and-drain and gate-and-source of the ESD protection device resulting in static capacitive gate coupling which is more calculable and controllable. The ratios of the capacitances are set so as to bias the gate of the ESD protection device above threshold during an ESD event, thus allowing the ESD protection device to sink current during the ESD event.

REFERENCES:
patent: 4423431 (1983-12-01), Sasaki
C. Duvvury et al. "Dynamic Gate Coupling of NMOS for Efficient Output ESD Protection," IRPS Proceedings, 1992, pp. 141-150.
S. Dabral, R. Aslett, and T. Maloney, "Core Clamps for Low Voltage Technologies," 1994, EOS/ESD Symposium Proceedings, pp. 141-149.

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