ESD protection device

Active solid-state devices (e.g. – transistors – solid-state diode – Bipolar transistor structure

Reexamination Certificate

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Details

C257S330000, C257S355000, C257S361000, C257S513000, C257S532000

Reexamination Certificate

active

07977769

ABSTRACT:
An ESD protection device is described, which includes a first P-type doped region, a second P-type doped region, a first N-type doped region, a second N-type doped region and an isolation structure. The first P-type doped region is configured in a substrate. The second P-type doped region is configured in the first P-type doped region. The first N-type doped region is configured in the first P-type doped region and surrounds the second P-type doped region. The second N-type doped region is configured in the substrate and surrounds the first P-type doped region. The isolation structure is disposed between the first P-type doped region and the second N-type doped region, wherein a spacing is deployed between an outward edge of the first N-type doped region and the isolation structure.

REFERENCES:
patent: 5181091 (1993-01-01), Harrington et al.
patent: 2004/0026728 (2004-02-01), Yoshida et al.
patent: 2010/0148265 (2010-06-01), Lin et al.

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