ESD protection circuit without overstress gate-driven effect

Details ESD protection circuit without overstress gate-driven effect ESD protection circuit without overstress gate-driven effect

1999-08-23

2001-06-19

Ballato, Josie (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C361S111000

Reexamination Certificate

active

06249410

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is related to electrostatic discharge (ESD) protection circuits for integrated circuits formed on a semiconductor substrate. More particularly, this invention relates to ESD protection circuits that have gate driven charge dissipation transistors.
2. Description of the Related Art
Electrostatic discharge (ESD) damage has become one of the main reliability concerns on the integrated circuit (IC) products. Especially, now that complementary metal oxide semiconductor (CMOS) technology has been developed into the deep-submicron lithographic feature size, the scaled-down metal oxide semiconductor (MOS) devices and thinner gate oxide has become more vulnerable to the extreme voltage level from contact with an ESD source. For general industrial specification, the input and output pins of the IC products have to sustain the extreme voltage level from contact with an ESD source of above 2000V. Therefore, the ESD protection circuits have to be placed around the input and output pads of the IC's to protect the IC's against the ESD damage, by shunting the electrostatic charges present at the ESD source from the IC's.
A typical input ESD protection circuit is shown in FIG.
1
. The input pad
5
is connected to the internal integrated circuits
15
and the ESD protection device
10
. When an ESD source is brought in contact with the input pad
5
the ESD protection device
10
is forced into an avalanche breakdown causing the ESD protection device to conduct dramatically, thus dissipating the electrostatic charge from the ESD source.
The ESD protection device
10
is a gate grounded n-type MOS (GGnMOS) transistor Mn
1
10
having its source, bulk, and gate connected to the substrate biasing voltage source VSS. The substrate biasing voltage source VSS may be an independent negative voltage source or the ground reference point. The drain of the GGnMOS transistor Mn
1
10
is connected to input pad
5
.
In order to sustain a high ESD current, the gate-grounded NMOS (often called GGnMOS) Mn
1
10
in
FIG. 1
is drawn with relatively a large device dimension, such as W/L=500 &mgr;m/0.5 &mgr;m in a typical 0.35 &mgr;m CMOS technology. With such a large device dimension, the GGnMOS transistor Mn
1
10
is typically drawn with multiple fingered of polycrystalline silicon gates. The typical layout example of the GGnMOS transistor Mn
1
10
for ESD protection as shown in
FIG. 2
had been described in “Methodology For Layout Design And Optimization Of ESD Protection Transistors,” S. G. Beebe, 1996 EOS/ESD Symp. Proc., pp.265-275.
The GGnMOS transistor Mn
1
10
is connected to the input pad
5
with the metal lands
20
. The metal lands
20
are connected to the N+ drain diffusion
25
of the GGnMOS transistor Mn
1
10
. The N+ source diffusions
30
are connected together and to the substrate biasing voltage source VSS. Multiple fingers
35
of heavily doped polycrystalline silicon form the gates of the GGnMOS transistor Mn
1
10
. The gates
35
of the GGnMOS transistor Mn
1
10
are connected through the metal land
40
to the substrate biasing voltage source VSS.
It has been found that the GGnMOS transistor Mn
1
10
having a relatively large device dimension can sustain only a relatively low ESD voltage level, because the multiple heavily doped polycrystalline silicon gates
35
cannot uniformly turn on the GGnMOS transistor Mn
1
10
during the extreme voltage level from contact with an ESD source as described in “Improving The ESD Failure Threshold Of Silicided NMOS Output Transistors By Ensuring Uniform Current Flow,” T. L. Polgreen et al., IEEE Trans. Electron Devices, vol. 39, pp. 379-388, 1992.
Since only some regions of the GGnMOS transistor Mn
1
10
are turned on, the charge to be conducted from the ESD source causes the current density within the channel of those turned-on regions to be large. This causes damage to several of the fingers of the gates of the GGnMOS transistor Mn
1
10
. So, even though the GGnMOS transistor Mn
1
10
has a relatively large device dimension, it is effectively a much smaller transistor that cannot sustain the large ESD current.
In order to improve the tolerance of the ESD protection device to the extreme voltage levels from the ESD source, the multiple heavily doped polycrystalline silicon gates
35
of the ESD protection NMOS transistor Mn
1
10
have to be uniformly turned on to share the current from the ESD source. If all the heavily doped polycrystalline silicon gates
35
of the ESD protection NMOS transistor Mn
1
10
can be uniformly turned on during the extreme voltage level from contact with an ESD source, the ESD protection NMOS transistor Mn
1
10
can sustain high levels of voltage from the ESD source as described by T. L. Polgreen et al.
To achieve the uniform turn-on behavior among the multiple heavily doped polycrystalline silicon gates
35
of the MOS transistor Mn
1
, a gate-driven technique is described in U.S. Pat. No. 4,855,620 (C. Duvvury et al.); U.S. Pat. No. 5,086,365 (C. -D. Lien); “Dynamic Gate Coupling Of NMOS For Efficient Output ESD Protection,” C. Duvvury et al., Proc. of IRPS, 1992, pp. 141-150; “Achieving Uniform NMOS Device Power Distribution For Submicron ESD Reliability,” C. Duvvury et al., Tech. Dig IEDM, 1992, pp. 131-134; “EOS/ESD Reliability Of Deep Sub-Micron NMOS Protection Devices,” S. Ramaswamy et al., Proc. of IRPS, 1995, pp. 284-291; “Capacitor-Couple ESD Protection Circuit For Deep-Submicron Low-Voltage CMOS ASIC,” M. -D. Ker et al., IEEE Trans. on VLSI Systems, vol. 4, pp. 307-321, September, 1996; and U.S. Pat. No. 5,631,793 (M. -D. Ker et al.).
This improves the tolerance of the MOS transistor Mn
1
to the extreme voltage levels from contact with the ESD source. The structure of a gate-driven input ESD protection circuit is shown in FIG.
3
. An ESD-detection circuit is connected from the input pad
5
to the gate of the ESD protection NMOS transistor Mn
1
10
. When the pad
5
is exposed to the extreme voltage level of an ESD source, the ESD-detection circuit
45
will generate a voltage VG to bias the gate of the ESD protection NMOS transistor Mn
1
10
. Therefore, the voltage level at the multiple heavily doped polycrystalline silicon gates
35
of the ESD protection NMOS transistor Mn
1
10
causes the ESD protection NMOS transistor Mn
1
10
to be uniformly turned on to dissipate the charge from the ESD source and allow the integrated circuit to withstand a higher voltage level present at the ESD source. A typical gate-driven design for an input ESD protection circuit is shown in
FIG. 4
, where the ESD-detection circuit can be simply realized by a capacitor C
50
and a resistor R
55
. The capacitor C
55
is connected from the input pad
5
to the gate of the ESD protection NMOS transistor Mn
1
10
and the gate of the ESD protection NMOS transistor Mn
1
10
is connected to the substrate biasing voltage source VSS through a resistor R
55
. The capacitor C
40
is used to couple the ESD transient voltage level of the ESD voltage source from the pad
5
to the gate of the ESD protection NMOS transistor Mn
1
10
. With a coupled voltage VG on the gate of the ESD protection NMOS transistor Mn
1
10
, all the heavily doped polycrystalline silicon gates
35
of the ESD protection NMOS transistor Mn
1
10
can be uniformly turned on to bypass the ESD current and dissipate the charge from the ESD source.
Therefore, the voltage level of the ESD source that the ESD protection NMOS transistor Mn
1
10
can sustain before failure can be effectively improved. To maintain the coupled voltage VG on the gate of the ESD protection NMOS transistor Mn
1
10
, a resistor Rn
55
is added from the gate of the ESD protection NMOS transistor Mn
1
10
to the substrate biasing voltage source VSS. When the ESD-transient voltage from the ESD voltage source connected to the input pad
5
is coupled through the capacitor C
50
to the gate of the ESD protection NMOS transistor Mn
1
10
, such coupled voltage VG is held longer in time as a result of t

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