ESD protection circuit with tunable gate-bias

Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means

Reexamination Certificate

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Details

C361S111000

Reexamination Certificate

active

07064942

ABSTRACT:
An ESD protection circuit with tunable gate-bias coupled between a first and second pads for receiving power supply voltages. The ESD protection circuit includes a diode, a resistor coupled between the cathode of the diode and the first pad, a capacitor coupled between the cathode of the diode and the second pad, a first transistor of a first conductivity type having a gate coupled to the cathode of the diode, a drain coupled to the anode of the diode and a source coupled to the second pad, a second transistor of a second conductivity type having a gate coupled to the cathode of the diode, a drain coupled to the anode of the diode and a source coupled to the first pad, and a third transistor of the first conductivity type having a gate coupled to the anode of the diode, a drain coupled to the first pad and a source coupled to the second pad.

REFERENCES:
patent: 5550497 (1996-08-01), Carobolante
patent: 5754388 (1998-05-01), Schmidt
patent: 6097229 (2000-08-01), Hinterscher
patent: 6249410 (2001-06-01), Ker et al.
patent: 6388850 (2002-05-01), Ker et al.
patent: 6628159 (2003-09-01), Voldman
patent: 6671153 (2003-12-01), Ker et al.
patent: 2002/0135565 (2002-09-01), Gordon et al.
patent: 2003/0139024 (2003-07-01), Ker et al.

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