ESD protection circuit with segmented buffer transistor

Details ESD protection circuit with segmented buffer transistor ESD protection circuit with segmented buffer transistor

1991-01-31

1992-10-20

DeBoer, Todd E.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

361 58, 361 91, 361111, H02H 904

Patent

active

051575736

ABSTRACT:
An electrostatic discharge protection circuit for an integrated circuit employing a segmented field effect buffer transistor between the input/output pad and the active devices on the integrated cicuit. An extended resistive structure is configured in series with the segmented buffer transistor and the input/output electrical contact pad. The extended resistive structure is integrally formed with the individual segments of the buffer FET. The resistive structure may be implemented as an extended n well structure adjacent the FET segments. In a first resistance mode during normal circuit operations, the extended resistive structure has a low resistance value and introduces virtually no additional load to the input/output buffer circuitry. In a second mode of operation during ESD discharge, the resistive structure has a second significantly higher resistance which reduces current values during the ESD event thereby protecting the buffer circuit. A thick oxide snap-back device is also employed to provide a parallel EDS discharge path with low power dissipation.

REFERENCES:
patent: 4086642 (1978-04-01), Yoshida et al.
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Chen et al., "The Effect of Channel Hot Carrier Stressing on Gate Oxide Integrity in MOSFET", Proc. Int'l Reliability Physics Symposium, 1988.
Khurana et al., "ESD on CHMOS Devices--Equivalent Circuits, Physical Models and Failure Mechanisms", Proc. Int'l. Reliability Physics Symposium, 1985.
Duvvury et al., "ESD Protection Reliability in 1 Micrometer CMOS Technologies", Proc. Int'l Reliability Physics Symposium 1986.
Weste et al., Principles of CMOS VLSI Design, Addison-Wesley Publishing Company, pp. 224-231.
Fujishin et al., "Optimized ESD Protection Circuits for High-Speed MOS/VLSI", Proc. Custom Integrated Circuits Conference May, 1984, pp. 569-573.
Ochoa et al., "Snap-Back: A Stable Regenerative Breakdown Mode of MOS Devices", IEEE Transactions on Nuclear Science, vol. NS-30, No. 6, Dec., 1983, pp. 4127-4130.
Avery, "Using SCR's As Transient Protection Structures in Integrated Circuits", RCA DSRC, Princeton, N.J., pp. 177-180.

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