ESD protection circuit for multi-power and mixed-voltage...

Details ESD protection circuit for multi-power and mixed-voltage... ESD protection circuit for multi-power and mixed-voltage...

2001-08-27

2004-12-07

Toatley, Jr., Gregory J. (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C361S111000

Reexamination Certificate

active

06829125

ABSTRACT:

BACKGROUND OF INVENTION
1. Field of Invention
The invention relates to an ESD protection circuit and, in particular, to an ESD protection circuit for a multi-power and mixed-voltage integrated circuit that can distinguish between a working voltage and an electrostatic voltage by the rise times of each of them.
2. Related Art
Electrostatic protection is an important issue in the study of integrated circuits (IC). The ESD (Electro Static Discharge) protection circuit is used to prevent chips from damage caused by static electricity, which accompanies a large current and a large voltage. Alternatively, many types of ICs are manufactured to include logic functions that operate at different voltage power supply levels. For example, a modern microprocessor chip may include core logic operating at a power supply voltage of 2.5 volts, which interfaces with input/output (I/O) circuitry operating with a 3.3 volts DC power supply. By way of further example, many floppy disk and hard disk controller ICs interface with ISA or EISA busses that require with a 5.0 volts power supply.
In general, separate power in a chip is used to avoid a noise coupling between “dirty” and “clean” busses. However, separate power would induce ESD weakness. For example,
FIG. 1
shows a case where I/O power is separate from that of an internal circuit
101
. A power supply Vcco is separated from a power supply Vcci, and the ground busses are separated such that a resistance Rsub exists between Vsso and Vssi. If an ESD pulse is applied to the pin
102
with respect to the power supply Vcci, the ESD current may discharge through path
103
. The path
103
is the desired current path of the ESD current. However, the resistance Rsub might be large enough to introduce a large IR voltage drop, resulting in a large voltage difference between the pin
102
and the power supply Vcci. When the voltage difference is too large, part of the internal circuit
101
is overstressed and then damaged, that is, an unexpected path
104
is initiated to discharge ESD current.
As shown in
FIG. 2
, an ESD protection circuit
205
is provided to connect the power supply Vcco and the power supply Vcci. The ESD current can be discharged easily through the parasitic diode D
1
and the ESD protection circuit
205
for the power supply Vcci, that is, the path
203
. In this case, the ESD current also could be discharged through path
204
to discharge the ESD current from a pin
202
to the power supply Vcci. An internal circuit
201
would not be damaged and could be protected safely. Thus, the ESD protection circuits
205
between separate power supply are very important to protect the internal circuit
201
.
In prior art, a back-to-back diode is used to serve as this kind of ESD protection circuit, as shown in FIG.
3
. The number of back-to-back diode depends on the requirement of noise immunity and the voltage difference between a power supply Vcc
1
and a power supply Vcc
2
. For example, while the nominal power supply Vcc
1
is the same as the power supply Vcc
2
and the power supply Vcc
1
is expected to be noisier than the power supply Vcc
2
, the number of back-to-back diode in the direction of the power supply Vcc
1
to the power supply Vcc
2
could be increased to enhance the noise immunity. However, the increased diode number would degrade the protection efficiency of the ESD protection circuit. Furthermore, while the power supply Vcc
1
is larger than the power supply Vcc
2
, the voltage drop of the diode string in the direction of the power supply Vcc
1
to the power supply Vcc
2
have to be larger than the voltage drop between the power supply Vcc
1
and the power supply Vcc
2
. For example at least 4 diodes (D
1
~D
4
), as shown in
FIG. 3
, have to compensate for a difference of 5 volts and 3.3 volts in the supply voltage.
As described above, a large number of diodes may be required in order to prevent the noise coupling between the different power supplies and would degrade the protection efficiency. In addition, this kind of ESD protection circuit has a potential circuit problem due to the power sequence dependent property as described below.
Nowadays, an IC may require many different power supplies, each being for one of a plurality of internal circuits and each being capable of independent operation. To save power, each of these internal circuits may be independently turned off and turned on based upon dynamically changing operational requirements. This power sequencing raises design problems. As one example, as shown in
FIG. 2
, during power saving modes, when the power supply Vcci is deactivated independently for power saving, the power from the energized power supply Vcco will flow to the un-energized power supply Vcci through the ESD protection circuits
205
such as those in FIG.
3
. The energizing of power supply Vcci is also undesired. Thus, if power sequencing is violated, current may flow from an energized rail to an un-energized rail causing a short or defeating the purpose of an energy saving mode.
From the above description, how to provide an ESD protection circuit for separating power supply and to overcome the noise between power supplies is currently an important subject.
SUMMARY OF THE INVENTION
Pursuant to the above problems, it is an objective of the invention to provide an ESD protection circuit, which is used for an IC with multi-power and mixed-voltage.
It is also another objective of the invention to provide an ESD protection circuit, which can lower the noise coupling and increase the protection efficiency.
To achieve the above objective, in one aspect, the circuit according to the invention includes a resistor device, a capacitor device, and a PMOS device. The resistor device is in series and connected between a power supply and the capacitor device. The capacitor device is connected in series between the resistor device and the ground. The PMOS device includes a gate electrode, a first electrode, a second electrode, and a bulk electrode. The gate electrode is connected between the resistor device and the capacitor device. The bulk electrode is interconnected to the first electrode, and the first electrode is connected to the power supply.
Generally, the ESD voltage is far larger than the normal power-on voltage, and the rise time of the ESD pulse and the rise time of the normal power-on pulse are, respectively, in nanosecond order and in millisecond order. As described above, a RC time constant of a RC circuit composed of the resistor device and the capacitor device is from 0.1 to 10 microseconds. Thus, the RC circuit could distinguish the ESD voltage and the normal power-on voltage. During a normal power-on event, the RC circuit could couple with the rise time of the normal power-on voltage pulse synchronously. However, during an ESD event, the RC circuit would be delayed so that the RC circuit could not couple with the rise time of the ESD voltage pulse synchronously. Due to the difference of the rise time, the RC circuit could control the on/off of the PMOS device. Therefore, the ESD protection circuit according to the invention is on in the ESD event to discharge ESD, and is off in the normal power-on event to prevent the current from flowing through the ESD protection circuit.
In another aspect of the invention, the circuit, which is carried out in a semiconductor device with multiple power supplies, includes at least two ESD protection circuits, and a common ESD bus. The resistor devices and the first electrodes of the ESD protection circuits are connected to at least two separate corresponding power supplies, respectively. The second electrodes of the ESD protection circuits are connected to the common ESD bus, respectively. The common ESD bus surrounds the whole semiconductor device and serves as the common connection among separate power supplies.
As described above, the current could not flow through the ESD protection circuits in a normal power-on event, so the noise between separate power supplies will not occurr. Alternatively, the current could flow through one of the ESD pro

Affiliated with

Also associated with

Rating

ESD protection circuit for multi-power and mixed-voltage... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with ESD protection circuit for multi-power and mixed-voltage..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and ESD protection circuit for multi-power and mixed-voltage... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3307048