ESD protection circuit for mixed-voltage I/O ports using...

Details ESD protection circuit for mixed-voltage I/O ports using... ESD protection circuit for mixed-voltage I/O ports using...

2005-06-07

2005-06-07

Sircus, Brian (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Transient responsive

C361S056000

Reexamination Certificate

active

06903913

ABSTRACT:
An ESD protection circuit for mixed-voltage input/output (I/O) circuits. The ESD protection circuit utilizes substrate triggering of a parasitic NPN BJT under a cascaded NMOS transistor pair with a current generated by a triggering current generator. The ESD protection circuit is triggered much faster. Under normal circuit operations, the triggering current generator can also endure high-voltage signals without overstressing internal components and retains good reliability.

REFERENCES:
patent: 5932918 (1999-08-01), Krakauer
patent: 5946177 (1999-08-01), Miller et al.
patent: 6140682 (2000-10-01), Liu et al.
patent: 6327126 (2001-12-01), Miller et al.
patent: 6657835 (2003-12-01), Ker et al.

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