ESD protection circuit for mixed-voltage I/O by using...

Details ESD protection circuit for mixed-voltage I/O by using... ESD protection circuit for mixed-voltage I/O by using...

2001-06-07

2003-12-02

Toatley, Jr., Gregory J. (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C361S111000, C361S117000

Reexamination Certificate

active

06657835

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The invention relates to an ESD (Electrostatic Discharge) protection circuit and, in particular, to an ESD protection circuit for mixed-voltage I/O by using stacked NMOS transistors with the substrate triggering technique.
2. Related Art
To construct a high circuit density and to achieve desired functions, MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) with shrinking dimensions have been widely used in advanced IC (Integrated Circuit) techniques. However, to satisfy the requirement of a constant field scaling, many IC techniques also scale down the power supply voltage. Therefore, an interface is required to connect semiconductors or sub-systems using different internal working voltages. Due to the mixed working voltages, the chip-to-chip interface I/O circuit must be designed to prevent electrical overstress and undesirable current leakage paths. The ESD circuit also has to satisfy similar conditions and constraints. One of the constraints is that the mixed-voltage I/O circuit is able to sustain voltages, which may be in excess of the gate oxide reliability requirement.
FIG. 1
shows an embodiment of the U.S. Pat. No. 5,932,918 “ESD protection clamp for mixed voltage I/O stages using NMOS transistors”. As shown in the drawing, the patent proposed to use stacked NMOS transistors
122
,
126
to limit the voltage on the I/O pad, protecting the internal circuit. The implementation of the stacked NMOS transistors
122
,
126
in CMOS manufacturing process is shown in FIG.
2
. The source of the transistor
122
and the drain of the transistor
126
share an intermediate N+ diffusion region. In such a structure, there is a parasitic lateral bipolar transistor.
FIG. 3
is a voltage-current breakdown characteristics of a single NMOS device and stacked NMOS devices. As shown in the drawing, the working voltages of the stacked NMOS transistors
122
,
126
in the breakdown region are almost twice as big as that of a single NMOS transistor. When the same ESD current flows through the stacked transistors, heat generated on the stacked NMOS transistors (Power=I * V) doubles that of a usual single NMOS device. Therefore, the stacked NMOS transistors are easily to-be burned out due to the ESD. In other words, the ESD robustness of the stacked NMOS devices is greatly decreased.
SUMMARY OF THE INVENTION
In view of the foregoing problems, an object of the invention is to provide an ESD protection circuit for mixed-voltage I/O by using stacked NMOS transistors with the substrate triggering technique to increase ESD protection capability for mixed-voltage I/O circuits.
The disclosed ESD protection circuit uses the substrate triggering technique to perform ESD protection on mixed-voltage I/O circuits. The ESD protection circuit contains: a set of stacked NMOS transistors with a first NMOS transistor and a second NMOS transistor, a parasitic lateral bipolar transistor, a substrate current generating circuit, and a parasitic substrate resistor. The drain of the first NMOS transistor connects to an I/O pad. The gate of the first NMOS transistor connects to a first working voltage. The source of the first NMOS transistor connects to the drain of the second NMOS transistor. The gate of the second NMOS transistor connects to an internal circuit. The source of the second NMOS transistor connects to a second working voltage. The collector of the parasitic lateral bipolar transistor connects to the drain of the first NMOS transistor and its emitter connects to the source of the second NMOS transistor. A first terminal of the substrate current generating circuit connects to the I/O pad, a second terminal connects to the second working voltage, and a third terminal connects to the substrate of the lateral bipolar transistor, so that a triggering current is sent out of the third terminal when the voltage at the I/O pad is over a predetermined value. One end of the parasitic substrate resistor connects to the base of the bipolar transistor and the other end connects to the second working voltage, using the triggering current to turn on the bipolar transistor.


REFERENCES:
patent: 5932918 (1999-08-01), Krakauer
patent: 6140682 (2000-10-01), Liu et al.
patent: 6433979 (2002-08-01), Yu
Ming-Dou Ker et al., “ESD Protection Design for Mixed-Voltage I/O Circuit with Substrate-Triggered Technique in Sub-Quarter-Micron CMOS Process”, Proceedings of the International Symposium on Quality Electronic Design, 2002, IEEE.

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