ESD protection circuit for integrated circuit

Details ESD protection circuit for integrated circuit ESD protection circuit for integrated circuit

1994-08-17

1997-02-04

DeBoer, Todd

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

361 91, 361111, H02H 904

Patent

active

056005253

ABSTRACT:
An ESD protection circuit includes a portion for protecting a pair of power lines and a portion for protecting an I/O pin. The power line protection portion includes at least three SCRs electrically connected in series between the power lines. A zener diode is electrically connected between a gate of the SCR at one end of the series and the negative power line, and a resistor is electrically connected between the gate of the one SCR and the positive power line. The gates of the other SCRs in the series are electrically connected to the negative power line or to their own cathode. The I/O pin protection portion includes a plurality of SCRs connected in series between the power lines with the I/O pin being connected between the SCR at one end of the series and the next adjacent SCR in the series. A separate zener diode is electrically connected between the gate of the SCR at the one end of the series and the gate of the next adjacent SCR and the negative power line. A separate resistor is connected between the gate of the SCR at the one end of the series and the next adjacent SCR and the positive power line. The gates of the other SCRs in the series are connected to the negative power line or to their own cathode.

REFERENCES:
patent: 3886432 (1975-05-01), Piccone et al.
patent: 4066918 (1978-01-01), Heuner et al.
patent: 4323942 (1982-04-01), Hartman et al.
patent: 4405933 (1983-09-01), Avery
patent: 4484244 (1984-11-01), Avery
patent: 5010380 (1991-04-01), Avery
patent: 5072273 (1991-12-01), Avery
patent: 5274262 (1993-12-01), Avery
patent: 5343053 (1994-08-01), Avery

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