ESD protection circuit for inside a power pad or...

Details ESD protection circuit for inside a power pad or... ESD protection circuit for inside a power pad or...

2011-03-08

2011-03-08

Nguyen, Danny (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C361S111000

Reexamination Certificate

active

07903380

ABSTRACT:
An electrostatic discharge (ESD) protection circuit configured completely inside one of a power pad and an I/O pad of an electronic circuit, the ESD protection circuit comprising an electrostatic discharge (ESD) circuit that, when activated, discharges an ESD from a first voltage bus to a second voltage bus. The second voltage bus is at a lower electrical potential than the first voltage bus. An ESD discharge control circuit in electrical connection with the ESD discharge circuit that controls the activation of the ESD discharge circuit and including an NMOS transistor and an electrical node. The NMOS transistor regulating a rate of voltage decay of the electrical node from a predetermined high voltage level to a lower voltage level, the regulation of the rate of voltage decay of the electrical node is non-linear. The activation of the ESD discharge circuit determined by the rate of voltage decay of the electrical node.

REFERENCES:
patent: 4791318 (1988-12-01), Lewis et al.
patent: 5508649 (1996-04-01), Shay
patent: 6147538 (2000-11-01), Andresen et al.
patent: 7027275 (2006-04-01), Smith
patent: 7098717 (2006-08-01), Watt
patent: 2006/0103998 (2006-05-01), Smith

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