ESD protection circuit for IC with separated power domains

Details ESD protection circuit for IC with separated power domains ESD protection circuit for IC with separated power domains

2007-10-10

2010-10-19

Leja, Ronald W (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

Reexamination Certificate

active

07817386

ABSTRACT:
An ESD protection circuit suitable for applying in an integrated circuit with separated power domains is provided. The circuit includes a P-type MOSFET coupled between a first circuit in a first power domain and a second circuit in a second power domain. A source terminal of the P-type MOSFET is coupled to a connection node for connecting the first circuit and the second circuit. A gate terminal of the P-type MOSFET is coupled to a positive power line of the second power domain. A drain terminal of the P-type MOSFET is coupled to a negative power line of the second power domain. A body terminal of the P-type MOSFET is also coupled to the connection node.

REFERENCES:
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patent: 7106562 (2006-09-01), Kitagawa
patent: 2004/0207021 (2004-10-01), Russ et al.
patent: 2006/0209478 (2006-09-01), Arai et al.
patent: 2006/0262472 (2006-11-01), Okushima
patent: 2008/0062597 (2008-03-01), Chen et al.
patent: 2008/0144244 (2008-06-01), Van Camp
Ker et al., “ESD Protection Design to Overcome Internal Damage on Interface Circuits of a CMOS IC with Multiple Separated Power Pins”, Sep. 2004, pp. 445-451, IEEE Transactions on Components and Packaging Technologies, vol. 27, No. 3.

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