ESD protection circuit for I/O buffers

Details ESD protection circuit for I/O buffers ESD protection circuit for I/O buffers

1997-05-02

1999-09-14

Leja, Ronald W.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

361111, H02H 400

Patent

active

059531908

ABSTRACT:
An electrostatic discharge (ESD) protection circuit for an output transistor coupled to an I/O pin of an integrated circuit, including a logic circuit having at least one data input, a tristate enable input, and an tristate output coupled to a gate node of the output transistor wherein the tristate output is placed in a high impedance state in response to the tristate enable input. The ESD protection circuit also includes a tristate enable circuit which drives the tristate enable input according to the presence or absence of an ESD event on the I/O pin. During normal operation, the tristate enable circuit applies a first logic level to the tristate enable input such that the tristate output of the logic circuit is placed in a low impedance state, and during an ESD event on the I/O pin, the tristate enable circuit applies a second logic level to the tristate enable input such that the tristate output of the logic circuit is placed in a high impedance state.

REFERENCES:
patent: 5570043 (1996-10-01), Churchill

Affiliated with

Also associated with

Rating

ESD protection circuit for I/O buffers does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with ESD protection circuit for I/O buffers, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and ESD protection circuit for I/O buffers will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1515972