ESD protection circuit for high-voltage, high DV/DT pads

Details ESD protection circuit for high-voltage, high DV/DT pads ESD protection circuit for high-voltage, high DV/DT pads

2005-10-04

2005-10-04

Leja, Ronald (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

Reexamination Certificate

active

06952333

ABSTRACT:
A pad that experiences a high-voltage, high dV/dT signal during normal operation is prevented from falsely triggering by utilizing a bipolar transistor connected to the pad to provide ESD protection, and a MOS transistor connected to the bipolar transistor to turn off the bipolar transistor during normal circuit operation.

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Albert Z.H. Wang, “On-Chip ESD Protection For Integrated Circuits”, An IC Design Perspective, 2002, pps. 46-47, no month.

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