ESD protection circuit employing channel depletion

Details ESD protection circuit employing channel depletion ESD protection circuit employing channel depletion

1988-01-19

1989-05-30

Pellinen, A. D.

Electricity: electrical systems and devices

Safety and protection of systems and devices

With specific voltage responsive fault sensor

361 56, 361 58, 361 88, 361 91, 361 92, 361111, 357 2313, 357 48, H02H 904

Patent

active

048356530

ABSTRACT:
An electrostatic discharge protection circuit includes a P.sup.- doped channel and an N.sup.- doped channel that form a serial path between a signal pad and a transistor. Holes are depleted from the P.sup.- doped channel in response to a negative electrostatic discharge on the input signal pad; and electrons are depleted from the N.sup.- doped channel in response to a positive electrostatic discharge on the input signal pad. When either depletion occurs, the path from the signal pad to its transistor is open circuited; and so the transistor is protected. Conversely, when no electrostatic charge exists on the signal pad, the path through the P.sup.- doped channel and the N.sup.- doped channel is highly conductive; and so signals pass between the pad and the transistor very quickly.

REFERENCES:
patent: 3395290 (1968-07-01), Farina et al.
patent: 3947727 (1976-03-01), Stewart
patent: 4086642 (1978-04-01), Yoshida et al.
patent: 4264941 (1981-04-01), London
patent: 4605980 (1986-08-01), Hartranft et al.
Sedra, Adel S. and Kenneth C. Smith, Microelectronic Circuits, 1982, p. 252.

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