ESD protection circuit and semiconductor device

Details ESD protection circuit and semiconductor device ESD protection circuit and semiconductor device

2011-06-21

2011-06-21

Nguyen, Danny (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C361S111000

Reexamination Certificate

active

07965482

ABSTRACT:
This disclosure concerns an ESD protection including logic gates connected between a first power input and a second power input, a second potential of the second power input lower than the first potential of the first power input, wherein in the logic gates, an output of the logic gate at a front stage are connected to an input of the logic gate at a rear stage, if a protection potential between the first and the second potentials is applied to a node connecting the output to the input when the logic gates respond to an ESD surge, a breakthrough current is carried to the logic gates from the first potential toward the second potential, and if the first and the second potentials are applied to the first power input and the second power input, logic values of the logic gates are kept in a constant state.

REFERENCES:
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patent: 7085113 (2006-08-01), Gauthier et al.
patent: 7295411 (2007-11-01), Arai et al.
patent: 7339770 (2008-03-01), Maloney et al.
patent: 7385383 (2008-06-01), Reddy et al.
patent: 11-017117 (1999-01-01), None

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