ESD protection circuit

Details ESD protection circuit ESD protection circuit

2001-03-16

2004-04-20

Patel, Rajnikant B. (Department: 2838)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Transient responsive

C361S521000

Reexamination Certificate

active

06724601

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a circuit for providing protection from electrostatic discharge (ESD) on an integrated circuit chip.
2. Related Art
ESD protection circuitry is well known to integrated circuit designers. In general, ESD protection circuitry is provided to protect the input/output circuitry and core circuitry of an integrated circuit from large and sudden discharges of electrostatic energy. Various ESD events include discharge between pads of the integrated circuit, between voltage supply terminals of the integrated circuit and between pads and voltage supply terminals of the integrated circuit. ESD protection circuitry has been designed to protect from ESD events that occur during testing and ESD events that occur during normal operation of the integrated circuit.
Examples of ESD protection circuits can be found in U.S. Pat. Nos. 5,740,000, 6,040,968, 6,125,021, 6,118,640, 5,825,603 and 5,956,219.
As the feature sizes of integrated circuits are scaled down, the various elements of the integrated circuits become more susceptible to damage from ESD events. It would therefore be desirable to have improved ESD protection circuits.
SUMMARY
Accordingly, the present invention provides an integrated circuit having an electrostatic discharge (ESD) protection circuit, a core protection circuit, a sensitive core circuit and peripheral circuitry. The ESD protection circuit is coupled between the V
DD
voltage supply terminal and the V
SS
voltage supply terminal, and is capable of providing protection to the peripheral circuitry. The ESD protection circuitry requires help from core protection circuit to protect the sensitive core circuit. The sensitive core circuit includes circuit elements that are particularly susceptible to ESD events, such as six-transistor SRAM cells.
The core protection circuit and the sensitive core circuit are coupled in series between the V
DD
and V
SS
voltage supply terminals, with the core protection circuit coupled to the V
DD
voltage supply terminal. The sensitive core circuit has a V
CC
voltage supply terminal coupled to receive a V
CC
supply voltage from the core protection circuit. The core protection circuit is configured to cause the V
CC
supply voltage to rise slowly with respect to a rising voltage on the V
DD
voltage supply terminal during power-on of the integrated circuit. The core protection circuit can further be configured to disconnect the V
CC
voltage supply terminal from the V
DD
voltage supply when a voltage on the V
DD
voltage supply terminal exceeds the nominal V
DD
supply voltage by a predetermined amount.
In a particular embodiment, the core protection circuit includes a p-channel transistor having a source coupled to the V
DD
supply terminal, a drain coupled to the V
CC
supply terminal, and a gate coupled to the V
SS
supply terminal. In this embodiment, the resistance of the p-channel transistor and the capacitance of the sensitive core circuit create an RC delay circuit having a time constant large enough to cause the p-channel transistor to turn on slowly during power on. As a result, the ESD protection circuit will have adequate time to turn on before current through the sensitive core circuit can become high enough to cause any damage to the sensitive core circuit. In another embodiment, a resistor can be added in parallel with the p-channel transistor, thereby enhancing the slow turn on of the p-channel transistor.
In another embodiment, the gate of the p-channel transistor is coupled to a switch control circuit, which uses a delay circuit to slow down the turn on of the p-channel transistor during power on. In yet another embodiment, the switch control circuit is configured to quickly turn off the p-channel transistor when the voltage on the V
DD
supply terminal exceeds a predetermined voltage during normal operation of the integrated circuit. In this case, the core protection circuit advantageously protects the sensitive core circuit from ESD events that occur during normal operating conditions.
The present invention will be more fully understood in view of the following description and drawings.


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