ESD protection circuit

Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means

Reexamination Certificate

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C361S111000

Reexamination Certificate

active

08077440

ABSTRACT:
An ESD protection circuit comprises a first supply line (VDD), a second supply line (Vss), an ESD protection device, preferably being configured as a transistor (MP), which is connected between the first and second supply line (VDD, VSS) and at least one pin (VA) connected to the first and second supply lines (VDD, VSS) via diodes D1, D2. The ESD protection device is controllable by a trigger voltage that is set by a trigger voltage setting circuit (RP, RD, Z1, Z2, Z3). The ESD protection circuit comprises a trigger circuit (1) being connected to the at least one pin (VA) and providing pin specific trigger voltages, wherein the trigger circuit (1) is further connected to the trigger voltage setting circuit.

REFERENCES:
patent: 6064249 (2000-05-01), Duvvury et al.
patent: 6577480 (2003-06-01), Avery et al.
patent: 6614633 (2003-09-01), Kohno
patent: 2005/0225912 (2005-10-01), Pant et al.
patent: 2008/0116519 (2008-05-01), Wilkening
patent: 10 2004 050767 (2006-04-01), None
patent: 01/11749 (2001-02-01), None
patent: 2005040211 (2006-04-01), None
patent: 2006040211 (2006-04-01), None
Feng, Haigang, et al; “An ESD Protection Circuit for Mixed Signal ICS”; IEEE Custom Integrated Circuits Conference (2001); pp. 493-496.
International Search Report for Int'l Appln. PCT/IB2008/052397 (Sep. 17, 2008).

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