Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means
Reexamination Certificate
2005-09-20
2005-09-20
Jackson, Stephen W. (Department: 2836)
Electricity: electrical systems and devices
Safety and protection of systems and devices
Load shunting by fault responsive means
C361S091100
Reexamination Certificate
active
06947268
ABSTRACT:
An ESD-protecting circuit is connected between a terminal pad and an internal circuit formed in an LSI. The ESD-protecting circuit includes a conductive line connected to the terminal pad; first and second protecting elements, connected to the conductive line; and first and second resistive elements formed on the. The conductive line has a slit that divides the conductive line so that the first and second resistive elements have equal resistive values.
REFERENCES:
patent: 5248892 (1993-09-01), Van Roozendaal et al.
patent: 5404041 (1995-04-01), Diaz et al.
patent: 5468984 (1995-11-01), Efand et al.
patent: 5594611 (1997-01-01), Consiglio et al.
patent: 5640299 (1997-06-01), Leach
patent: 5763919 (1998-06-01), Lin
patent: 5854504 (1998-12-01), Consiglio
patent: 5859456 (1999-01-01), Efand et al.
patent: 5917220 (1999-06-01), Waggoner
patent: 6362497 (2002-03-01), Hiraga
patent: 6587320 (2003-07-01), Russ et al.
S. Wolf, 1990, Silicon Processing for VLSI ERA, v.2, Process Integration, Lattice Press, pp. 180-187.
Jackson Stephen W.
Kitov Zeev
Oki Electric Industry Co. Ltd.
Volentine Francos & Whitt PLLC
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