ESD parasitic bipolar transistors with high resistivity...

Details ESD parasitic bipolar transistors with high resistivity... ESD parasitic bipolar transistors with high resistivity...

2003-05-13

2004-09-07

Smith, Matthew (Department: 2825)

Active solid-state devices (e.g., transistors, solid-state diode

Bipolar transistor structure

Plural non-isolated transistor structures in same structure

C438S208000, C438S355000

Reexamination Certificate

active

06787880

ABSTRACT:

BACKGROUND OF INVENTION
1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to the fabrication of an Electro Static Discharge (ESD) device and more particularly an Electro Static Discharge (ESD) device using a silicide process.
2) Description of the Prior Art
The n-type MOS transistor has been widely employed as the primary component for an ESD protection circuit in semiconductor IC devices. It is well known that silicidation of the drain and LDD junctions reduce ESD performance significantly. Most salicided process have a removal option which allows unsalicided areas (e.g., resistors) to be formed.
NMOS transistors stacked in a cascade configuration provide robust ESD protection for mixed voltage I/O in both silicided and silicide-blocked technologies. However, this kind of device has high snapback voltage. Also, the high snapback voltage of the stacked NMOS degrades its IT
2
(IT
2
is the second breakdown trigger current)) since the power dissipation is great. The IT
2
is the current at or before the MOS gets into secondary breakdown (thermal/permanent damages) The higher the It
2
, the more robust the NMOS and the higher the ESD threshold. For the process technology where the suicide block and abrupt junction steps were are not available, a biasing network was necessary to ensure uniform triggering of all fingers. So, the need for high voltage tolerant I/O's severely complicates ESD protection.
FIG. 5A
shows a single poly N-MOS device that is used in the prior art as an ESD device. The structure and snap back mechanism are described below. The single-poly N-MOS device is shown in cross section and layout in FIG.
5
A.
FIG. 5B
shows a top plan view.
FIG. 5C
shows the IV curve and snap back curve for the ESD device. Vsp is the snapback holding voltage.
FIG. 5D
shows the electrical schematic of the device in FIG.
5
A. When a short-duration (100 to 110 ns) constant current pulse is applied to the drain with the source and gate tied to the substrate (substrate grounded), the device should have the I-V characteristic shown in FIG.
5
C. At normal operation, the device is off because the gate is grounded. When the drain breakdown voltage, BVdss is reached, current starts to flow as a result of impact ionization of die reverse-biased drain junction. At current It
1
, and voltage Vt
1
, the device triggers into snapback. The trigger current It
1
and voltage is related to the channel length and BVdss. Note that the trigger point (Vt
1
, It
1
,) is not the same as BVdss. BVdss, usually is defined as the drain junction avalanche breakdown voltage at a specified drain current density. The trigger point is the point that has the highest voltage just before snapback. The snapback region of the I-V curve is roughly linear and, therefore, may be represented by a snapback voltage Vsb and a differential resistance Rsb. The snapback voltage Vsb is defined as the linear extrapolation of the snapback region back to zero current. Care must be taken to avoid defining Vb and Rb by extrapolating from low current values near the point where the I-V curve changes slope from negative to positive. Therefore, the values of Vsb and Rsb were obtained from measurements made at high currents with the transmission-line pulse technique. Because the high-current values are relevant to ESD events, we need to use them rather than the low-current values when designing for protection against ESD. With sufficiently high current It
2
, flowing in the snapback region, the device triggers into second breakdown. We define a second trigger point (Vt
2
, It
2
) corresponding to the triggering from snapback into second breakdown. Second breakdown is the term used for power bipolar devices to indicate the regime of thermal runaway and current-instability.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering: U.S. Pat. No. 5,898,205 (Lee), U.S. Pat. Nos. 5,519,242 (Avery), U.S. Pat. No. 5,969,923 (Avery), U.S. Pat. No. 5,559,352 (Hsue et al.), U.S. Pat. No. 5,043,782 (Avery) and U.S. Pat. No. 5,689,113 (Li et al.).
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a structure and a method for fabricating an Electro Static Discharge (ESD) device using a NMOS transistor structure there the collector of the parasitic bipolar Transistor has high resistivity regions that increase the resistivity of the collector.
To accomplish the above objectives, the present invention provides a structure and a method for an ESD device. The invention is an ESD device (e.g., parasitic bipolar transistor) that has the structure of a N-MOS transistor and a p+ substrate contact. The source and drain of the MOS transistor form the collector and base of the ESD's parasitic bipolar transistor. The device preferably has silicide regions over the doped regions. The ESD device is a parasitic bipolar NPN Tx. The invention has high resistivity regions within the collector of the parasitic NPN (e.g., drain of the FET). The invention has two embodiments (preferred types) of high resistivity regions: 1) isolation regions (e.g., oxide shallow trench isolation (STI)) and 2) high resistance (e.g., lightly doped regions or undoped, (e.g., channel regions)). The channel regions can have gates thereover and the gates can be charged. Also, optionally a n
−
well (n minus well) can be formed under the collector/drain. The high resistivity regions increase the collector resistivity thereby improving the performance of the ESD device.
The invention's Electro Static Discharge (ESD) device preferably comprises:
a first doped region and a second doped region in a substrate; the first and second doped regions have a first conductivity type dopant;
at least a high resistivity region at least partially surrounded at the substrate surface, by the first doped region;
a first gate over a first channel region; the first channel region between the first and the second doped regions;
a third doped region separated from the second doped region by an isolation region; the third doped region has a second conductivity type dopant.
Additional objects and advantages of the invention will be set forth in the description that follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of instrumentalities and combinations particularly pointed out in the append claims.


REFERENCES:
patent: 5043782 (1991-08-01), Avery
patent: 5519242 (1996-05-01), Avery
patent: 5559352 (1996-09-01), Hsue et al.
patent: 5689133 (1997-11-01), Li et al.
patent: 5898205 (1999-04-01), Lee
patent: 5969923 (1999-10-01), Avery
Amerasekera et al., “Correlating Drain Junction Scaling, Salicide Thickness, and Lateral NPN Behavior, with the ESD/EOS Performance of a 0.25 &mgr;m CMOS Process,” 1996 IEEE, IEDM 96-893 to 96-896.
Charvaka Duvvury, “ESD: Design for IC Chip Quality and Reliability,” 2000 IEEE, pp. 251-259.
Polgreen et al., “Improving the ESD Failure Threshold of Silicided n-MOS Output Transistors by Ensuring Uniform Current Flow,” IEEE Trans. on Electron Devices, vol. 39, No. 2, Feb. 1992, pp. 379-388.
Notermans et al., “The Effect of Silicide on ESD Performance,” IEEE 1999, 37th Annual Int'l Reliability Physics Syop., San Diego, CA, pp. 154-158.
Chen et al., “Design Methodology and Optimization of Gate-Driven NMOS ESD Protection Circuits in Submicron CMOS Processes,” IEEE Trans. on Electron Devices, vol. 45, No. 12, Dec. 1998, pp. 2448-2456.

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