ESD network with capacitor blocking element

Details ESD network with capacitor blocking element ESD network with capacitor blocking element

1999-12-30

2002-08-13

Huynh, Kim (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

With tuned circuit

C361S111000, C361S056000

Reexamination Certificate

active

06433985

ABSTRACT:

FIELD OF THE INVENTION
This invention pertains to electrostatic discharge (ESD) protection circuits. In particular, this invention pertains to an ESD protection network with a series blocking capacitor element to prevent overvoltage of a thin dielectric receiver gate structure by blocking ESD caused voltage spikes.
BACKGROUND OF THE INVENTION
As CMOS technology dimensions are scaled down, electrostatic discharge events become more disruptive and more difficult to control. Thinner dielectrics become more susceptible to damage from ESD events and the protective circuits themselves are constrained due to size limitations. Another difficulty arises due to the increased operational frequencies of IC chips which approach typical frequency levels of ESD events. Attenuating and/or shunting ESD frequency spectra while simultaneously passing information signals becomes a challenge when designing useful ESD protection networks. The present invention is directed to providing an ESD protection network that reduces voltage levels of ESD pulses, and to selectively block frequency components of ESD pulses.
SUMMARY OF THE INVENTION
An ESD protection network is described which prevents high voltage oxide stress. A first embodiment consists of a filter network (such as a series blocking capacitor) and diode protection elements. The general ESD network described is shown in FIG.
1
. The illustrated filter network can be designed for several types of ESD protection functions. It can be designed to provide voltage reduction for ESD pulses, and to selectively block the frequency components of ESD pulses.
An IC chip having an input that may be subjected to an ESD event is an environment where the present invention can be usefully implemented. The present ESD protection network is coupled to an IC input for attenuating an ESD event occurring on the input node and for passing to the IC chip received input signals. The ESD protection network includes a series capacitor between the input and the IC chip receiver for attenuating the ESD frequencies.
Any devices that include components susceptible to overvoltage stress caused by an ESD event could also usefully implement the present inventive protection network. An ESD event that generates frequencies lower than an operational frequency of a device can be shunted or substantially attenuated by a series capacitor coupled between a node undergoing an ESD event and the device while passing operational frequencies of the device.
Other features and advantages of this invention will become apparent from the following detailed description of the presently preferred embodiment of the invention, taken in conjunction with the accompanying drawings.


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IBM Technical Disclosure Bulletin, vol. 30, No. 8, Jan. 1988 pp. 389-390.

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