ESD improvement with dynamic substrate resistance

Details ESD improvement with dynamic substrate resistance ESD improvement with dynamic substrate resistance

2011-08-30

2011-08-30

Patel, Dharti (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C361S118000

Reexamination Certificate

active

08009399

ABSTRACT:
In some embodiments, an electrostatic discharge (ESD) protection circuit includes a substrate resistance control circuit coupled to a body of a first NMOS transistor. The substrate resistance control circuit increases a resistance of the body of the first NMOS transistor during an ESD event. The first NMOS transistor has a drain coupled to an input/output (I/O) pad and a gate coupled to a first voltage source. The first voltage source is set at ground potential.

REFERENCES:
patent: 6424510 (2002-07-01), Ajit et al.
patent: 6465768 (2002-10-01), Ker
patent: 6566715 (2003-05-01), Ker et al.
patent: 2010/0128401 (2010-05-01), Lai et al.

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