Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – With pn junction isolation
Reexamination Certificate
2002-02-04
2004-03-30
Zarabian, Amir (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
With pn junction isolation
C257S173000, C257S361000, C257S362000
Reexamination Certificate
active
06713841
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to an ESD structure for an integrated circuit.
An ESD guard structure is described in Design and Layout of a High ESD Performance NPN Structure for Submicron BiCMOS/Bipolar Circuits (J. Chen et al., Proceedings of the IEEE IRPS (1996), p. 227 ff).
Circuits that are integrated in a chip contain guard structures for protecting the inputs or outputs (I/O ports) against electrostatic overvoltages and consequent electrostatic discharges (ESD). These ESD guard structures are disposed between the input pad of the integrated circuit and the input or output terminals requiring protection. Given interference by a parasitic overvoltage, the ESP guard structure switches through to divert the parasitic overvoltage impulse. In extreme cases, such overvoltage impulses can lead to the destruction of the integrated circuit.
But with the constantly greater miniaturization in semiconductor technology, it is becoming more and more difficult to provide ESD guard structures that detect this kind of parasitic overvoltage impulse. Particularly in contemporary and future CMOS technologies, because of the small window width between the operating voltage and the breakdown voltage of the elements of the integrated circuits, it is very important that the corresponding ESD guard structures switch on precisely and reproducibly within an extremely narrowly defined voltage range.
FIG. 1
shows an ESD guard structure of the species where the guard element is triggered by a series circuit including a breakdown diode and a resistor (Also see Chen et al.).
FIG. 1
shows an integrated circuit
1
that is connected to a terminal pad
3
via a connecting line
2
. An ESD guard structure
4
is disposed between the terminal pad
3
and the integrated circuit
1
. The ESD guard structure
4
in
FIG. 1
consists of a protective transistor
5
having a load path connected between the line
2
and the terminal
6
that is charged with a reference potential VSS. A series circuit including a trigger diode
7
and a resistor
8
is connected in parallel to the load path of the protective transistor
5
. The center tap
9
of this series circuit is connected to the control terminal of the protective transistor
5
. If the voltage at the terminal pad
3
exceeds the breakdown voltage of the trigger diode
7
, the control terminal of the protective transistor
6
is actuated via the potential at the center tap
9
such that the protective transistor
5
and the guard structure
4
are switched on.
But the production of such a trigger diode having an optimally definable and reproducible breakdown voltage is problematic. Furthermore, the value of the breakdown voltage must not fluctuate too greatly in different ESD guard structures.
The trigger diode is also required to have an optimally small leakage current in the off state.
Therefore, an n+/p+ Zener diode is frequently utilized as the trigger diode. Very low breakdown voltages can be achieved with such trigger diodes, however, a very large leakage current is disadvantageously generated. On the other hand, trigger diodes with weakly doped p+ regions and/or n+ regions, and thus with smaller leakage currents, exhibit extremely high breakdown voltage values.
Another problem is that the breakdown voltage values of the trigger diodes are usually adjustable only by adjusting the dopant concentrations, which sometimes interferes greatly in the functionality of the remaining circuit elements (i.e. protective transistor, resistor) of the ESD guard structure.
Thus, lateral trigger diodes are frequently employed, which are created by aligning a p+ region relative to the corresponding n+ region. The p+ region and the n+ region are arranged at a small distance away from each other. In lateral trigger diodes such as this, the breakdown voltage can be easily adjusted exclusively by layout measures. Nevertheless, because of the limited alignment precision of these layout measures, undesirable (that is to say, unacceptable) fluctuations of the breakdown voltage usually occur.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide an electro-static discharge guard structure having a trigger diode, and a method of producing the trigger diode which overcomes the above-mentioned disadvantages of the prior art apparatus and methods of this general type.
In particular, it is an object of the invention to provide an ESD guard structure of the above-described type whose trigger diode has an optimally low breakdown voltage and a small leakage current. Furthermore, the breakdown voltage of this trigger diode will be adjustable with optimal precision and is not subject to large fluctuations.
With the foregoing and other objects in view there is provided, in accordance with the invention, an electro-static discharge guard structure for protecting an integrated circuit. The guard structure includes: a terminal pad and an electrically conductive connection connecting the terminal pad to the integrated circuit; a terminal connected to a reference potential; a guard element having a load path connected between the terminal pad and the terminal; and a lateral trigger diode having a breakdown voltage. The trigger diode is for switching the guard element through when the breakdown voltage is exceeded. The trigger diode is configured between the control terminal of the guard element and the terminal pad. The guard structure also includes a gate electrode having a length and a width. The trigger diode includes an anode zone and a cathode zone. The anode zone and the cathode zone are aligned with respect to the gate electrode. The anode zone and the cathode zone are spaced apart a distance corresponding to a dimension selected from the group consisting of the width of the gate electrode and the length of the gate electrode.
In accordance with an added feature of the invention, the guard element is a thyristor or a transistor.
In accordance with an additional feature of the invention, the trigger diode is a Zener diode with a low breakdown voltage.
In accordance with another feature of the invention, the trigger diode is a PIN switching diode with a low breakdown voltage.
In accordance with a further feature of the invention, the width or the length of the gate electrode is at least twice as large as the maximum alignment precision.
In accordance with a further added feature of the invention, there is provided, a switching device for adjusting the breakdown voltage of the trigger diode. The switching device is connected to the gate electrode.
In accordance with a further additional feature of the invention, the gate electrode at least partially consists of polysilicon.
In accordance with yet an added feature of the invention, the anode zone has a very high dopant concentration; and the cathode zone has a very high dopant concentration.
With the foregoing and other objects in view there is also provided, in accordance with the invention, method for producing the trigger diode in the ESD guard structure, which includes steps of: providing a semiconductor having a surface and having the gate electrode disposed on the surface; forming a first mask on a region of the surface such that the first mask has a mask edge that is configured directly over the gate electrode; incorporating dopant of a first conductivity type into unmasked regions of the surface, and then dissolving the first mask; forming a second mask on other regions of the surface such that the second mask has a mask edge that is configured over the gate electrode; and incorporating dopant of a second conductivity type into unmasked regions of the semiconductor body, and then dissolving the second mask.
In accordance with an added mode of the invention, ion implantation is used to perform the step of incorporating the dopant of the first conductivity type; and ion implantation is used to perform the step of incorporating the dopant of the second conductivity type.
In accordance with an additional mode of the invention, a
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Soward Ida M.
Stemer Werner H.
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